Job Locations: Hyderabad
Total vacancies: 0
– Requires understanding of Verilog/uvm/vmm/ system verilog
– Ability to understand verification flow/assertions/ccheckers and update the flow
– Run regressions and get code/functional coverage
– Implement the new testcases/coverage numbers
To apply for this position, please either enter your details along with the updated resume in the right hand side panel OR send your updated resume directly to firstname.lastname@example.org with current CTC, expected CTC and notice period details. Our team will contact you for further details.