Bhanu Prakash

Bhanu Prakash is Semiconductor Industry veteran since last 20+ years. He is Btech from IIT BHU, Varanasi in Electronics and Communication Engineering. His work span covers Telecom, VLSI Design, CAD Flow and Methodology. Working with Motorola and ST Microelectronics, he has hands on worked across complete Hardware design tasks like IP Design and Verification, Chip Implementation & Signoff. He has special interest in Debug and all Signoff related tasks (like Formal Checks, TA, Low Power checks etc). He nurtured a team of experts covering Full RTL2GDSII at ST Micro Noida Office. He holds a trade secret and has authored/reviewed multiple papers related to Chip Design and Design for Cost Initiatives.

Here is the summary of the key projects completed by him.

  • Board Design with FPGA for Trunk Call Unit of E10B Telephone Exchange
  • 30 Channel PCM Equipment Debug Improvements
  • IP Design and Verification of Serial Access Protocol, Host Controller Interface, Content addressed Memory.
  • Expertise in all Unix scripting language
  • Creation of Kits around following tools: Design Compiler/RTL Compiler/ Formality/Conformal.
  • Ownership of SoC Design Flow at ST Micro, working with Europe counter-parts.
  • Experience in Top Level Chip Budgeting and Chip assembly flow
  • Implemented Channel Less Chip Design Flow saving around 10% of Chip area.
  • Worked as Technology Interface with fab Units of ST
  • Created new Methods to reduce (10%) Clock Insertion Delay
  • Created new methods to reduce (upto 15%) Design area.
  • Proficiency in driving Training and Skill Improvement work-shops
  • Liasoning and followup with external stake holders
  • Creation of CAD Budget for ST Microelectronics, G Noida