DVB T2/T/S2/S and C Demodulator IP

Description

DVB-T/T2/C/S2 IP is a highly optimized multi standard DVB-T/T2/C/S/S2 Decoder solution designed for next generation satellite, cable and terrestrial digital television reception. DVB-T/T2/C/SS2 IP converts demodulated I/Q signals into a bit stream for use by the video decoder. This includes all de-interleaving, FEC decoding and output processing.dvbtss2

Features

    • DVB-T2 demodulation:
    • Compliant with ETSI EN-302755 v1.2.1
    • DTG7 v3 and Nordig Unified v2.4 compliant
    • 1.7, 5, 6, 7 and 8 MHz normal and extended BW signals supported
    • GS streams, FEF and MISO supported
    • DVB-T demodulation:
    • Compliant with ETSI EN-300744 v1.5.1
    • DTG7 v3 and Nordig Unified v2.4 compliant
    • 6, 7 and 8 MHz BW supported
    • DVB-C demodulation:
    • Compliant with ETSI EN300429
    • Nordig Unified v2.4 and SARFT compliant
    • Up to 7.2 Ms/s symbol rate
    • DVB-S and S2 demodulation:
    • Compliant with ETSI EN300421 and
    • EN302307
    • Symbol rates from 1 to 45 Ms/s
    • Enhanced FEC for DVB-S and DirecTV legacy transmissions
    • DVB-T/T2 and DVB-C compatible with zero-,high- and legacy-IF tuners (CAN or silicon)
    • DVB-S/S2 compatible with zero-IF tuners (CAN or silicon)
    • Embedded microcontroller (DVB-T2 task sequencing by firmware and monitoring)
    • ADC for RF signal strength indicator
    • Flexible clock management for advanced power saving
    • JTAG and I?C serial bus interfaces
    • I2C repeater for private tuner communications
    • Advanced low-power CMOS process
    • 3.3-V, 2.5-V and 1.1-V power supplies with internal SMPS for 1.1-V generation
    • Typical power consumption 912 mW (DVB-T2 mode)
    • TQFP80 10x10x1 mm3 package with EPD

Benefits

    • Error correction capabilities - Robustness
    • Error concealment capabilities - Quality
    • Compliance to Allegro reference streams

Deliverables

  • Verilog Source RTL Code plus Simulation Environment
  • C Source Code
  • Physical Design scripts - Synopsys synthesis
  • Hardware simulation test bench with regression test suit
  • Reference platform drivers