I2C IP

Description

The I2C is a two-wire, bi-directional serial bus, which provides a simple and efficient method of short distance data transmission between many devices. The DI2CMS core provides an interface between a microprocessor/microcontroller and an I2C bus. It can work as a master or a slave transmitter/receiver - depending on a working mode, determined by the microprocessor/microcontroller. The DI2CMS coreincorporates all features required by the latest I2C specification, including clock synchronization, arbitration, multi-master systems and a high-speed transmission mode (the DI2CMS supports all the transmission speed modes).Built-in timer allows operation from a wide range of the clk frequencies. The DI2CMS is technology independent, that's why a VHDL or VERILOG design can be implemented in a variety of process technologies. Furthermore, it can be also completely customized in accordance to the customer's needs. The DI2CMS is delivered with fully automated testbench and complete set of tests, allowing easy package validation at each stage of SoC design flow. The I2C-bus supports any IC fabrication process (NMOS, CMOS, bipolar). Two wires, serial data (SDA) and serial clock (SCL), carry information between devices connected to the bus. Each devices is recognised by a unique address – whether it is a microcontroller, LCD driver, memory or keyboard interface. It can operate as either transmitter or receiver, depending on the function of the device. Obviously an LCD driver is only a receiver, whereas a memory can both receive and transmit data. In addition to transmitters and receivers, devices can also be considered as masters or slaves when performing data transfers (see Figures below). A master is the device which initiates a data transfer on the bus and generates the SCL clock signals. A slave is the device addressed by a master. The I2C-bus is a multi-master bus. This means that more than one device capable of controlling the bus can be connected to it. As masters are usually microcontrollers or microprocessors. i2c-ms

Features

    • Conforms to v.3.0 of the I2C specification
    • Master mode
    • Master operation
    • Master transmitter
    • Master receiver
    • Support for all transmission speeds
    • Standard (up to 100 kb/s)
    • Fast (up to 400 kb/s)
    • Fast Plus (up to 1 Mb/s)
    • High Speed (up to 3,4 Mb/s)
    • Arbitration and clock synchronization
    • Support for multi-master systems
    • Support for both 7-bit and 10-bit addressing formats on the I2C bus
    • Build-in 8-bit timer for data transfers speed adjusting
    • Slave mode
    • Slave operation
    • Slave transmitter
    • Slave receiver
    • Supports 3 transmission speed modes
    • Standard (up to 100 kb/s)
    • Fast (up to 400 kb/s)
    • Fast Plus (up to 1 Mb/s)
    • High Speed (up to 3,4 Mb/s)
    • Allows operation from a wide range of input clock frequencies
    • User-defined data setup time
    • User-defined timing (data setup, start setup, start hold, etc.)
    • Simple interface allows easy connection to microprocessor/microcontroller devices
    • Interrupt generation
    • Available system interface wrappers:
    • AMBA - APB Bus
    • Altera Avalon Bus
    • Xilinx OPB Bus
    • Fully synthesizable
    • Static synchronous design
    • Positive edge clocking and no internal tri-states
    • Scan test ready

Benefits

    • D-I2C-MS

Applications

    • Embedded microprocessor boards
    • Consumer and professional audio/video
    • Home and automotive radio
    • Low-power applications
    • Communication systems
    • Cost-effective reliable automotive systems

Deliverables

  • Source code:
  • VHDL Source Code or/and
  • VERILOG Source Code or/and
  • Encrypted, or plain text EDIF
  • VHDL & VERILOG test bench environment
  • Active-HDL automatic simulation macros
  • ModelSim automatic simulation macros
  • Tests with reference responses
  • Technical documentation
  • Installation notes
  • HDL core specification
  • Datasheet
  • Synthesis scripts
  • Example application
  • Technical suppor
  • IP Core implementation support
  • 3 months maintenance
  • Delivery the IP Core updates, minor and major versions changes
  • Delivery the documentation updates
  • Phone & email support

Tech Specs