Rakesh Adhikari (CEO)

Rakesh Adhikari is Semiconductor Industry veteran since last 17+ years, He has started his career with Motorola India as a design Engineer in year January 2000 after completing his Master’s degree from Delhi College of Engineering in Electronics and Communication Engineering and B.Tech from Kumaon Engineering College Dwarahat in 1998. After Motorola he joined a semiconductor services startup company RF Silicon Pvt Ltd and worked in the capacity of India Head Operations and Delivery. In 2013 May, to pursue his entrepreneurship dream he joined Incise Infotech Pvt Ltd as Director and now he is working as CEO and heading Incise Infotech Pvt. Ltd, to develop Semiconductor IP’s and provide SOC and IP design and Verification Services.

He is enabling and delivering cost effective Semiconductor Services in the following domains:

  • IP/SoC Design & Verification: Verilog, VHDL, System Verilog, C Based Verification, RTL Design/Integration , FPGA
  • IP and VIP Design: Verilog, VHDL, UVM, OVM
  • Physical Design: STA, Synthesis, DFT, PnR, DRC, LVS, LEC
  • Custom Design: Custom Memory/Standard cell/ Analog layout,Circuit design and Characterization
  • Virtual Prototyping: SystemC/TLM 2.0, C, C++
  • Embedded System : Bluetooth Low Energy, IoT, Product Validation & testing
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Vipin Latiyan (CTO)

16+ yrs of experience in the software development with wide domain knowledge of banking application and ERP packages. He is part of Incise core team, who is delivering most advanced technology solutions to Industry and the latest tools and technology to the Academia. He has expertise in latest cutting edge technologies like ASP, .NET, WCF, Visual Basic, PHP, MySQL, Android and Java Applications. During his career he has conceptualized, architected , designed and delivered banking solutions and ERP packages which are used and running in many companies. At Incise he has established the IT division and he driving young engineers to deliver some of the world’s best design solutions.

Here is the summary of the key projects completed by him.

  • Architect of Core Banking Solution at Incise
  • Technical Head of all technical developments
  • BankSys24 (Core Banking Solution)
  • BankMill (Core Banking Solution)
  • Data Synchronization
  • Sync Server
  • Facility Manager for Windows Mobile 5.0
  • Tour Watch Pocket PC (VB.NET)
  • Facility Manager (Visual Basic 6.0)
  • Inspection Manager (Visual Basic 6.0)
  • TourWatch XT (Visual Basic 6.0)
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Vishal Jain(Director Engineering – RTL Design & Verification)

Vishal has over 19 years of experience in Frontend Design & Verification. More recently, he was driving key activities on methodologies for Functional Verification. He has also managed DFT design and verification, Flow for IP’s and SOC’s in Imaging Division of STMicroelectronics, India. He has Master of Engineering in Microelectronics from Birla Institute of Technology and Science, India. His main area of Interest are Project Management, Advanced Functional Verification Methodologies, System Design and Verification especially UVM based Verification and Emulation / Acceleration for speeding up the verification signoff.

Here is the summary of the key projects completed by him.

  • SOC Verification strategy and its execution
  • Imaging SOC Definition, Design, Integration and Verification
  • Imaging Signal Processor Yushan, Shortbread, Xushan3, SELA
  • Writing DFT Specification, RTL, Verification plan, test cases for sensor project.
  • Integration of PCI-ISA, PCI-LAN-PCI-USB, PCI-IRDA to make PCI subsystem using make scripts.
  • Timers, DMA, SG-DMA, Interrupt Controller, PCI Bridges, SPI slave, Flash Controller, Clock and Reset Manager.
  • ARM Cortex M series, 8051 eWARP
  • Deployment of IP-XACT based tools at IP and SOC level.
  • Generation of XML using legacy RTL
  • Verilog, VHDL, System Verilog, SystemC, C, C++, Shell, TCL, PERL, Python
  • Expertise in all Unix scripting language
  • SOC Toos: Lint/CDC/DFT checks from synopsys,Design Compiler/RTL Compiler/ Formality/Conformal.
  • Ownership of SoC Design/Verification Flow at ST Micro, working with Europe counter-parts.
  • Proficiency in driving Training and Skill Improvement work-shops
  • Liasoning and followup with external stake holders
  • Project Sync, SVN, Perforce, GIT
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Atul Dogra (Director Engineering-Physical Design)

Atul Dogra is Semiconductor Industry veteran since last 20+ years. He is B.Tech from Delhi Institute of Technology, Delhi in Controls & Instrumentation Engineering. His work span covers VLSI Design, CAD Flows and Methodology, Foundry certification and Flow automation. Working with Motorola, Freescale and Mentor Graphics, he has hands-on experience across complete Hardware design tasks like IP/SoC physical design, Chip Design/Implementation & Signoff flows. He has special interest in innovating/driving Signoff methodologies and flow tasks (like TA, Low Power checks, Crosstalk effects, Signal Electromigration checks, Design for Manufacturing/Yield checks, Lithrography checks etc.). He nurtured a team of experts covering various aspects of Full RTL2GDSII flows and SoC Design at Freescale Noida Office. He has authored/reviewed multiple papers related to Chip Design flows and holds a patent and trade secret award.

Here is the summary of the key projects completed by him.

  • Chip Design driving from Planning to Sign-off implementation including LVS/DRC
  • Physical Design of numerous IPs
  • Experience in Top Level Chip Budgeting and Chip assembly flowExpertise in all Unix scripting language
  • Innovated/Driven various new Methodologies and their introduction in RTL2GDSII flow
  • Ownership/Creation of Flow automation kits for Floorplanning and Signal Integrity
  • Lead Signal Integrity Flows world-wide across Freescale
  • Lead Parasitic Extraction Flows world-wide across Freescale
  • Managed Design for Manufacturing methodology team for Freescale, India
  • Managed Testchip design team responsible for driving Test vehicles for upcoming technologies for Freescale, India
  • Managed Product Engineering group IC design at Mentor Graphics, India
  • Expertise in all Unix scripting language
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Charge Pump PLL IP

Charge Pump PLL IP

Description

This Charge Pump PLL is designed in CMOS LP technology, using seven metallization levels. These voltage pulses are converted to current pulses in the Charge Pump. These current pulses charge or discharge the Loop Filter to generate the control voltage for the VCO. The VCO generates a frequency (FVCO) proportional to this control voltage. This frequency is then divided by the Loop Frequency Divider, to generate FBCLK. 1467182555pll_300

Features

    • Input frequency (MHz): 19.2-40MHz
    • VCO frequency: 1500-3000MHz
    • Output frequency: PHI: 23.4375-1500MHz
    • Uses LVT and SVT devices in GO1 and SVT25 devices in GO2
    • Area: 0.1788 mm2 (Target) (X = 208 m, Y =860 m)
    • Maximum power: 15.22 mW
    • Fractional mode supported
Seven metal level technology used for design:
    • 4X (thin) metals
    • 0Y (intermediate) metals
    • 2Z (thick) metals

Applications

    • Used in frequency synthesis applications

Deliverables

  • Detailed Specification and Integration guide
  • LEF abstract
  • GDSII layout and Mapping files
  • LVS compatible netlist
  • Verilog-A Model
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Posted in PLL

Clock Generator (28nm) PLL IP

Clock Generator (28nm) PLL IP

Description

Clock generator PLL is designed to multiply an input clock signal by an integer 40 and 50. The output is 2.5GHz with 50% duty cycle with quadrature phases. Available in TSMC90LP, TSMC 65G, TSMC 28HPC, GF 28SLP20160520085552-main-tc_pll

Features

  • Input Reference Frequency range - 48MHz - 62.5MHz (90nm), 100MHz (65nm)
  • Output frequency range - 1.9GHz - 2.5GHz (Quadrature O/Ps)
  • Feedback divider value - 40 – 50 (90nm)
  • Output duty cycle - 50% +/- 3%
  • Period Jitter (P-P) - Under NDA
  • Power dissipation (nom) - Under NDA
  • Reset Pulse width (min) - 2us
  • Lock time (Max) - 3us
  • Area - Under NDA
  • Number of PLL supply pkg pins - 2
  • Supply Voltage - 1.2V(Typ) +/- 0.1V (90nm, 65nm), 1V (28nm)
  • Technology Option - TSMC90LP, TSMC 65G, TSMC
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Posted in PLL

Charge Pump PLL (CMOS40) IP

Charge Pump PLL (CMOS40) IP

Description

On the basis of its architecture its belongs to the class of Charge Pump PLLs. The key blocks in this architecture are mentioned in the following sections.

Phase/Frequency Detector

This block compares the phase difference between the corresponding rising edges of INFIN(buffered version of the Input Frequency Divider output) and FBCLK (buffered clock output from the Loop Frequency Divider), by generating voltage pulses with widths proportional to the input phase error.

Charge Pump and Loop Filter

Charge Pump converts the voltage pulses from the Phase/Frequency Detector to current pulses, which charge the Loop Filter and generate the Control Voltage for the Voltage Controlled Oscillator.

Voltage Controlled Oscillator

This is the oscillator inside the PLL, which produces a frequency output (FVCO) proportional to the input control voltage.Loop Frequency Divider Frequency Divider is present within the PLL for dividing VCO frequency (FVCO) by a factor called the Loop Division Factor (LDF). The output of this block is the FBCLK.

Input Frequency Divider

This Frequency Divider divides the PLL input frequency by a factor called the Input Division Factor (IDF). The output of this block is INFIN.

Output Frequency Divider

PLL output PHI is generated by dividing the FVCOBY2 clock (VCO clock divided by 2) by a factor called Output Division Factor (ODF). The divider that divides the FVCOBY2 to generate PHI is called Output Frequency Divider.

Lock Circuit

LOCKP signal is asserted high when the PLL enters the state of Coarse Lock, in which the average output frequency (for last 64 cycles of INFIN) is within ±10% (approximately) of the desired frequency. LOCKP signal is refreshed after every 64 cycles of INFIN. This is generated based on the result of the comparison of number of FBCLK cycles in a window of 58 INFIN cycles. The different cases generated after comparison are the following: If LOCKP is at L, then it goes to H in the next refresh cycle, if the number of FBCLK cycles in the 58 cycle INFIN window is 52 to 64. Otherwise, LOCKP stays at L. If LOCKP is at H, then it goes to L in the next refresh cycle, if the number of FBCLK cycles in 58 cycle INFIN window is less than 48 or higher than 68. Otherwise, LOCKP stays at H

Features

    • Input frequency: 6 MHz - 350 MHz
    • VCO frequency (FVCO): 1000 MHz - 2000 MHz
    • Output frequency (PHI): 7.93 MHz - 1000 MHz
    • Area: 0.1499259 mm2
    • Maximum power: 5.46 mW

Applications

  • Used in frequency synthesis applications
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Posted in PLL

16b Delta Sigma Stereo Audio ADC IP

16b Delta Sigma Stereo Audio ADC IP

This 16 bit ADC is a complete low cost stereo, audio Analog-to-Digital converter includes digital decimating filter, a third order (Mash2-1) Delta- Sigma ADC, a dc-removal filter. This device is fabricated on 40nm CMOS process, where high speed precision analog circuits are combined with high density logic circuits.

Features

  • 16 BIT STEREO AUDIO ADC AUDIO INTERFACE
  • DC-Removal FILTER
  • 3.3 V/1.1 V analog/digital power supply respectively
  • Zero phase error between channels
  • Linear phase digital filtering
  • Power down mode (auto analog shutdown)
  • Dc Attenuation upto -120dB
  • FSYNC and SCK internally generated

Deliverable

  • Detailed Specification and Integration guide
  • LEF abstract
  • GDSII layout and Mapping files
  • LVS compatible netlist
  • Verilog-A Model
Sample Description
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10b-1MSPS SAR ADC IP

10b-1MSPS SAR ADC IP

Description

This is a successive approximation 10 bit Analog-to-Digital converter. The 10-bit, high speed, low power, 8-channel, successive approximation ADC. The part operates from a single 3.3 V power supply and features throughput rates up to 1 MSPS.The device contains a low noise, wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 20 MHz.This ADC uses advanced design techniques to achieve very low power dissipation at high throughput rates. The architecture allows for high-performance, low-power ADCs to be packaged in small form factors for today's demanding applications 1467096941sar-adc

Features

    • Output is 10 bit Parallel
    • Conversion time/Sampling frequency = 1 us/1Msps
CLOCK REQUIREMENT
    • 2.5 MHz- 20 MHz
SUPPLY REQUIREMENT
    • 3.3 V Analog/1.1 V Digital
PERFORMANCE
    • INL < +/- 1 LSB
    • DNL < +/- 0.8 LSB
    • OTHER FEATURES
    • Continuous conversion mode
    • Discrete conversion mode

Deliverables

  • Detailed Specification and Integration guide
  • LEF abstract
  • GDSII layout and Mapping files
  • LVS compatible netlist
  • Verilog-A Model
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10b-160MHz ADC (802.11 AC AFE) IP

10b-160MHz ADC (802.11 AC AFE) IP

This ADC is a Dual Low area, Low Power 160 MHz,10 bit Pipelined Analog-to-Digital converter with complete internal reference.

Features

  • Output is 10 bit Parallel
  • Conversion rate: 160 MHz max
  • Differential Input = 1.0 Vp-p
  • Low Power/Low Resolution Modes available
  • Latency = 3.5 cycles
  • Complete Internal reference/No need for any package pin or external decoupling capacitor.

Deliverables

  • Technical documents
  • Design Guide
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