Skills: System Verilog
Job Locations: Hyderabad
Total vacancies: 0
– Requires some decent understanding of perl/sed/any shell scripting
– Makefile would be plus.
– This work requires simulation/synthesis understanding.
– Understanding of Verilog/systemveriloig code is a must.
– Syntheis (is optional). If you have it is good other wise .. it can be taught during the job.
– The candidate should be enthusiastic and willing to go beyond and learn the stuff to perform.
– Can be in range of 1-5 years experience.
To apply for this position, please either enter your details along with the updated resume in the right hand side panel OR send your updated resume directly to email@example.com with current CTC, expected CTC and notice period details. Our team will contact you for further details.