SPI-Quad IP

Description

DCD’s IP Core is a technology independent design that can be implemented in a variety of process technologies. The DQSPI system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. The system can be configured as a master or a slave device. Data rates as high as CLK/2, when other vendors’ solutions offer just CLK/8. Clock control logic allows a selection of clock polarity, phase and a choice of four fundamentally different clocking protocols to accommodate most available synchronous serial peripheral devices. When the SPI is configured as a master, software selects bit rates for the serial clock. The DQSPI automatically drive selected by SSCR (Slave Select Control Register) slave select outputs (SS7O – SS0O) and address SPI slave device to exchange serially shifted data. Error?detection logic is included to support interprocessor communications. A write collision detector indicates when an attempt is made to write data to the serial shift register while a transfer is in progress. A multiple-master mode fault detector automatically disables DQSPI output drivers, if more than one SPI device simultaneously attempts to become bus master. The DQSPI supports two DMA modes: single transfer and multi?transfer. These modes allow DQSPI to interface to higher performance DMA units, which can interleave their transfers between CPU CYCLESor execute multi-ple byte transfers. DQSPI is fully customizable, which means it is delivered in the exact configuration to meet users’ requirements.

Features

    • Operates with 8, 16 and 32 bit CPUs
    • Full duplex synchronous serial data transfer
    • DMA support
    • Support for 32, 16 and 8 bit systems
    • Support for various system Bus Standards
    • Single, Dual and Quad SPI transfer
    • Multimaster system supported
    • Optional FIFO size extension (128, 256, 512B)
    • Up to 8 SPI slaves can be addressed
    • Software Slave Select Output – SSO ? selection
    • Automatic Slave Select outputs assertion during each byte transfer
    • System error detection
    • Bit rate in fast SPI Mode ½ CLK
    • Four transfer formats
    • Simple SPU and DMA interface
    • Fully synthesizable, static synchronous de-sign with no internal tri?states

Benefits

    • D-Quad-SPI

Applications

    • Embedded microprocessor boards
    • Consumer and professional audio/video
    • Home and automotive radio
    • Low-power applications
    • Communication systems
    • Digital multimeters

Deliverables

    • Source code:
    • VHDL Source Code or/and
    • VERILOG Source Code or/and
    • Encrypted, or plain text EDIF
    • VHDL & VERILOG test bench environment
    • Active-HDL automatic simulation macros
    • ModelSim automatic simulation macros
    • Tests with reference responses
    • Technical documentation
    • Installation notes
    • HDL core specification
    • Datasheet
    • Synthesis scripts
    • Example application
    • Technical support
    • IP Core implementation support
    • 3 months maintenance
    • Delivery the IP Core updates, minor and major versions changes
    • Delivery the documentation updates
    • PHONE& email support

Tech Specs

  • D-Quad-SPI