Vishal Jain(Director Engineering – RTL Design & Verification)

Vishal has over 19 years of experience in Frontend Design & Verification. More recently, he was driving key activities on methodologies for Functional Verification. He has also managed DFT design and verification, Flow for IP’s and SOC’s in Imaging Division of STMicroelectronics, India. He has Master of Engineering in Microelectronics from Birla Institute of Technology and Science, India. His main area of Interest are Project Management, Advanced Functional Verification Methodologies, System Design and Verification especially UVM based Verification and Emulation / Acceleration for speeding up the verification signoff.

Here is the summary of the key projects completed by him.

  • SOC Verification strategy and its execution
  • Imaging SOC Definition, Design, Integration and Verification
  • Imaging Signal Processor Yushan, Shortbread, Xushan3, SELA
  • Writing DFT Specification, RTL, Verification plan, test cases for sensor project.
  • Integration of PCI-ISA, PCI-LAN-PCI-USB, PCI-IRDA to make PCI subsystem using make scripts.
  • Timers, DMA, SG-DMA, Interrupt Controller, PCI Bridges, SPI slave, Flash Controller, Clock and Reset Manager.
  • ARM Cortex M series, 8051 eWARP
  • Deployment of IP-XACT based tools at IP and SOC level.
  • Generation of XML using legacy RTL
  • Verilog, VHDL, System Verilog, SystemC, C, C++, Shell, TCL, PERL, Python
  • Expertise in all Unix scripting language
  • SOC Toos: Lint/CDC/DFT checks from synopsys,Design Compiler/RTL Compiler/ Formality/Conformal.
  • Ownership of SoC Design/Verification Flow at ST Micro, working with Europe counter-parts.
  • Proficiency in driving Training and Skill Improvement work-shops
  • Liasoning and followup with external stake holders
  • Project Sync, SVN, Perforce, GIT