Description
The MiPHYA c4.0 macrocell is extracted from production chips, it implements the lower (physical) layer protocols of the following standards:
- USB 3.0 SuperSpeed
- PCI-e 3.0
- SATA gen1/2/3
Data transmission and reception are provided over a dual differential pair CABLE. The TX (transmit) and RX (receive) serial channels operate plesiochronously (NRZ). The macro-cell can be used in Host or Device applications.
Features
-
- Serial transceiver (physical layer)
- Serializer and deserializer
- Direct support for USB3.0 SuperSpeed at 5.0 Gbit/s
- Direct support for 6.0 Gbit/s SATA
- 2.5 and 5.0 Gbit/s PCI Express operation
- Embedded oscillator
- High-performance PLL
- 20-bit parallel interface
- SSC modulation
- Comma detect to provide word alignment of incoming serial stream
- Requires DC-balanced encoding scheme
- Integrated impedance adaptation to transmission line characteristics
- Serial TX buffer with programmabl amplitude, pre-emphasis and slew rate
- OOB signaling
- JTAG test access port allows Internal loop-back for self-test
- Random pattern auto-test
- 1.1 V power supply -5 / +10%
- 1.8 or 2.5 V power supply +/- 10%
Integrated BIST allows:
-
- Self test of the macrocell in loop back mode at Gigabit rate on production testers
- Self test of the macrocell at system level, either in internal/external loop back mode or between different chips in transmission mode
Applications
-
- USB 3.0 SuperSpeed
- PCI-e 3.0
- SATA gen1/2/3 Transmission schemes encoding octets a 10-bit code groups to form a DC-balanced stream
- High-performance backplane interconnect
Deliverables
- GDSII layout and layer map files with Abstract with size and pin locations (lef)
- Verilog-a, CDL, encrypted Spectra netlist with Verification reports and environment Test cases, bring-up plans, coverage Re- ports
- System level simulation model for channel simulations