• Architecture, Specification and Micro-Architecture development
  • Reusable RTL Design for Low Power, Minimum Area and Maximum Speed
  • Synthesis, Timing Clean RTL, CDC, LINT
  • Verilog, VHDL, System Verilog
  • RTL Integration, 3rd Party IP Integration
  • ARM, ARC, 8 Bit Processors, Starcore
  • Timing constraints, Low power Clocking, Analog + Digital SOC
  • FPGA to ASIC Migration, FPGA Prototyping & Validation
  • UFS 2.0 , EMMC, SD USB 3.0 Interlaken ,DDR3.0, PCI Express, AHB, AXI ,MIPI, UniPro, M-PHY, ARM, Bluetooth , Wireless, DVB-H/T , Generic ARC Control Platform