Broadcast IP
DVB S2X/T2/C Demod+H264 STB SoC White Box IP
DVB T2/T/S2/S and C Demodulator IP
Description
DVB-T/T2/C/S2 IP is a highly optimized multi standard DVB-T/T2/C/S/S2 Decoder solution designed for next generation satellite, cable and terrestrial digital television reception. DVB-T/T2/C/SS2 IP converts demodulated I/Q signals into a bit stream for use by the video decoder. This includes all de-interleaving, FEC decoding and output processing.
Features
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- DVB-T2 demodulation:
- Compliant with ETSI EN-302755 v1.2.1
- DTG7 v3 and Nordig Unified v2.4 compliant
- 1.7, 5, 6, 7 and 8 MHz normal and extended BW signals supported
- GS streams, FEF and MISO supported
- DVB-T demodulation:
- Compliant with ETSI EN-300744 v1.5.1
- DTG7 v3 and Nordig Unified v2.4 compliant
- 6, 7 and 8 MHz BW supported
- DVB-C demodulation:
- Compliant with ETSI EN300429
- Nordig Unified v2.4 and SARFT compliant
- Up to 7.2 Ms/s symbol rate
- DVB-S and S2 demodulation:
- Compliant with ETSI EN300421 and
- EN302307
- Symbol rates from 1 to 45 Ms/s
- Enhanced FEC for DVB-S and DirecTV legacy transmissions
- DVB-T/T2 and DVB-C compatible with zero-,high- and legacy-IF tuners (CAN or silicon)
- DVB-S/S2 compatible with zero-IF tuners (CAN or silicon)
- Embedded microcontroller (DVB-T2 task sequencing by firmware and monitoring)
- ADC for RF signal strength indicator
- Flexible clock management for advanced power saving
- JTAG and I?C serial bus interfaces
- I2C repeater for private tuner communications
- Advanced low-power CMOS process
- 3.3-V, 2.5-V and 1.1-V power supplies with internal SMPS for 1.1-V generation
- Typical power consumption 912 mW (DVB-T2 mode)
- TQFP80 10x10x1 mm3 package with EPD
Benefits
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- Error correction capabilities - Robustness
- Error concealment capabilities - Quality
- Compliance to Allegro reference streams
Deliverables
- Verilog Source RTL Code plus Simulation Environment
- C Source Code
- Physical Design scripts - Synopsys synthesis
- Hardware simulation test bench with regression test suit
- Reference platform drivers
DVB T2/T Demodulator IP
Description
This DVB-T/T2 Demodulator IP supports all the new terrestrial specifications, including Rotated constellations, Alamouti, TFS and multiple PLP. Its performance meets or exceeds the most recent requirements. The IP features dual I/Q ADC's. It can work with different external RF tuner chips and CAN tuners thanks to a highly flexible RF interface and a dedicated programmable block.
Features
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- Compliance with DVB-T2 standard
- 1k, 2k, 4k, 6k, 16k, 32k FFT sizes.
- 1/32, 1/16, 1/8,1/4, 1/128, 19/128, 19/256 Guard Intervals.
- All Pilot Patterns PP1--?PP8.
- By PLP code rates: 1/2, 3/5, 2/3,3/4 4/5, 5/6.
- Constellations: QPSK, 16 QAM, 64 QAM, 256 QAM.
- 16K and 64K LDPC
- P1, P2, L1 and L2 reception and decoding.
- Channel bandwidths: 1.7 MHz, 5MHz, 6 MHz, 7MHz, 8MHz
- Output
Benefits
-
- Silicon proven
- Used in millions of devices
Deliverables
- Verilog Source RTL Code plus Simulation Environment
- C Source Code
- Physical Design scripts - Synopsys synthesis
- Hardware simulation test bench with regression test suit
- Reference platform drivers
DVB T/C Demodulator SoC White Box IP
ATSC3 Demodulator IP
Fully compliant with A/321 and A/322 ATSC3.0 standard -Support FDM / TDM / LDM -Maximum 64 PLPs (with extra TINT memory) Leading all three plug-fest test with our equipment's -1st : 2015.11, Sanghai, China -2nd : 2016.3, Baltimore, US -3rd : 2016.10, Jeju, Korea (we host this with ETRI)
Features:
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- Tested in real broadcasting environment.
- KBS/MBC/SBS are using our equipment for field-measurement
- Conducted field test several times with MBC/SBS
- Conducted a plug-fest lead by government institution with KBS
- Well balanced S/W and H/W partitioning
- Easy to upgrade or add new feature
- Cortex M3 are sufficient to control
- Very highly optimized
- Fitted in single mid-sided FPGA(Virtex7 690T)
- Single port ram are mainly used for silicon area
- Ready to ASIC
- Not using any other IP
- Need only memory conversion to ASIC