8259-Interupt Controller IP

Description

The D8259 is a soft Core of Programmable Interrupt Controller. It is fully compatible with the 82C59A device. Our efficient IP core can manage up to 8-vectored priority interrupts for the processor. Moreover, you can also program it to cascade and gain up to 64 vectored interrupts. And if it's not enough, you can always get more than 64 vectored interrupts. Just program our IP Core to the Poll Command Mode. The D8259 can operate in all 82C59A modes and it supports all 82C59A features. The D8259 Package includes fully automated testbench. Thanks to complete set of tests, you can easily validate the whole package at each stage of SoC design flow.

Features

    • 8 vectored priority interrupts
    • Up to sixty-four vectored priority interrupts with cascading
    • Support for all 82C59A modes features
    • MCS-80/85 and 8088/8086 processor modes
    • Fully nested mode and special fully nested mode
    • Special mask mode
    • Buffered mode
    • Pool command mode
    • Cascade mode with master or slave selection
    • Automatic end-of-interrupt mode
    • Specific and non-specific end-of-interrupt commands
    • Automatic and Specific Rotation
    • Edge and level triggered interrupt input modes
    • Reading of interrupt request register (IIR) and in-service register (ISR) through data bus
    • Fully synthesizable HDL Source Code
    • Static design and no internal tri-states

Applications

    • Embedded microprocessor boards

Deliverables

  • VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF
  • VHDL & VERILOG test bench environment Active-HDL automatic simulation macros
  • ModelSim automatic simulation macros Tests with reference responses
  • Technical documentation Installation notes HDL core specification Datasheet
  • Synthesis scripts Example application Technical support

SLIC IP

Description

This is a SLIC device specifically designed for wireless local loop (WLL) and ISDN terminal adaptors (ISDN-TA) and VoIP applications. One of the distinctive characteristic of this device is the ability to operate with a single supply voltage (from 5.5 V to 12 V) and self generate the negative battery by means of an on chip DC/DC converter controller that drives an external MOS switch. The battery level is properly adjusted depending on the operating mode. A useful characteristic forthese applications is the integrated ringing GENERATOR. The control interface is a parallel type with open drain output and 3.3 V logic levels. Constant current feed can be set from 20 mA to 40 mA. Off-hook detection threshold is programmable from 5 mA to 9 mA. The metering pulses are generated on chip starting from two logic signals (0 and 3.3 V) one define the metering pulse frequency and the other the metering pulse duration. An on chip circuit then provides the proper shaping and filtering. Metering pulse amplitude and shaping (rising and decay time) can be programmed by external components. A dedicated cancellation circuit avoid possible codec input saturation due to metering pulse echo.

Features

    • Monochip subscriber line interface circuit (SLIC) optimised for WLL and VoIP applications
    • Implement all key features of the BORSHT function
    • Single supply (5.5 V to 12 V)
    • Built in DC/DC converter controller
    • Soft battery reversal with programmable transition time.
    • On-hook transmission.
    • Programmable off-hook detector threshold
    • Metering pulse generation and filter
    • Integrated ringing
    • Integrated ring trip
    • Parallel control interface (3.3 V logic level)
    • Programmable constant current feed
    • Surface mount package
    • Integrated thermal protection
    • Dual gain value option
    • BCD III S, 90 V technology
    • -40 to +85 °C operating range

Deliverables

  • Configurable RTL Code
  • HDL based test bench and behavioral models
  • Test cases
  • Protocol checkers, bus watchers and performance monitors
  • Configurable synthesis shell
  • Documentation
  • Design Guide
  • Verification Guide
  • Synthesis Guide

LVDS TX PHY IP

Description

This is a physical layer for LVDS TX. It consists of six differential channels and supports 167.86 Mbps to 1.25Gbps data rate.

Features

    • LVDS Tx compliant with EIA/TIA-644 LVDS
    • Up to 1.25Gbps/lane data rate
    • 3.3V/1.2V power supply
    • Configurable common mode voltage
    • Supports reduced swing mode
    • Supports loop back test mode
    • Supports metal option TBD
    • Used devices - Core voltage RVT-NMOS/PMOS, Diode, 3.3V OD-NMOS/PMOS, Diode, NMOS cap, BJT, Un-silicided poly resister

Deliverables

  • Datasheet
  • Integration guideline
  • GDSII or Phantom GDSII
  • Layer map table
  • CDL netlist for LVS
  • LEF
  • Verilog behavior model
  • Liberty timing model
  • DRC/LVS/ERC results

The DEEPROM performs communication and exchanges data between external serial EEPROM Memory and CPU’s RAM memory interface.

EEPROM Controller IP

Description

The DEEPROM performs communication and exchanges data between external serial EEPROM Memory and CPU’s RAM memory interface. Its contents are accessible to the CPU in the same manner as a common SRAM memory, but require READY input to expand the time access. Our proprietary core allows to map serial EEPROM in processor memory space and control it as the parallel memory. The controller automatically sends all control instructions and read /write memory locations. As for the CPU, the EEPROM is being connected to it through the DEEPROM. Moreover, it's visible and controlled as parallel SRAM with long access time. Our unique Core has been designed to operate with popular 25XXX SPI Serial EEPROMs (Atmel, Microchip).

Features

    • Standard memory interface with ready control
    • Configurable SPI parameters
    • Serial clock prescaler
    • SPI mode
    • CS hold/setup
    • Updating bits in EEPROM status register
    • Simple interface allows easy connection to microcontrollers
    • Fully synthesizable, static design with no internal tri-states

Applications

    • Connection of Serial EEPROM to CPU
    • Non-volatile data storing

Deliverables

  • VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF
  • VHDL & VERILOG test bench environment Active-HDL automatic simulation macros
  • ModelSim automatic simulation macros Tests with reference responses
  • Technical documentation Installation notes HDL core specification Datasheet
  • Synthesis scripts Example application Technical support
The DEEPROM performs communication and exchanges data between external serial EEPROM Memory and CPU’s RAM memory interface.

SMART Card Interface IP

Description

The DSMART is a fast, versatile and cost-competitive core intended for smart card reader applications. It provides a communication interface with a smart card, based on ISO 7816-3/EMV4.2 requirements. DCD’s IP Core implements the hardware support for both T0 character oriented protocol and T1 block oriented protocol. It’s been designed to combine highly reduced CPU utilization and low area consumption, it is able to activate and deactivate cards, perform resets, handle ATR reception and many additional features. Configuration options enable user to adjust the DSMART to his needs and choose the proprietary options, which will be the most suitable for his design. Data transfer to and from the host system can be interrupt-driven or executed through Direct Memory Access (DMA). The automatic convention detection and decoding mechanism ensure the exact result regardless of the used convention. Elementary Time Unit (ETU) - time duration of the one bit is decoded from the received ATR interface byte and generated automatically. The card clock divider provides non-gated clock with a wide range of possible frequencies. There’s been also a special power down modeimplemented, in which the card clock is being hold in two possible states, depending on the card parameter. Error signaling and character repetition are automatic for the T0 protocol. The DSMART incorporates also an optional CRC/LRC hardware checking and generation mechanism which gives the convention independent result. The received CRC/LRC is not stored in the FIFO, but can be read in a case of CRC/LRC error. Also the optional block length counter provides security of the DMA block transfer and automatic CRC/LRC, subjoining with a manual affixing option. The special block mode handles block transfer automatically. Status and error registers provide necessary information about the FIFO state, errors and card events.

Features

    • Compatible with the ISO 7816-3: 2006 and EMV 4.1 standard
    • Support for asynchronous Smart Cards
    • Dual configurable length FIFO with two programmable thresholds
    • Card detection input
    • Software-configurable interrupts
    • Automatic convention detection and decoding
    • Programmable non-gated card clock generator
    • Automatic ETU generator
    • DMA support for transmit and receive
    • Hardware CRC and LRC calculations
    • Card power down mode with clock stop high and clock stop low possibility
    • Special fast block mode for T1 protocol (optional)
    • CRC/LRC hardware generation and checking
    • Byte counter with automatic CRC/LRC affixing(optional)
    • No inertial tri-state buffers
    • Fully synchronous synthesizable design

Applications

    • General purpose smart card readers
    • SO-7816 / EMV Bridges
    • Personal Wireless devices & SIM Readers in Telecom
    • Payphones and vending machines
    • Personal identification
    • Satellite TV security
    • Health care records storage

Deliverables

  • VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF
  • VHDL & VERILOG test bench environment Active-HDL automatic simulation macros
  • ModelSim automatic simulation macros Tests with reference responses
  • Technical documentation Installation notes HDL core specification Datasheet
  • Synthesis scripts Example application Technical support

Smart Card Controller IP

Description

Smart card controller core is compliant to ISO 7816 3 specification. The core is a technology independent, fully synchronous design. The controller functions at 2 –66 Mhz. The design provides a simple, timing friendly front end interface which enables easy integration of the core to controllers and other application specific front end logic. The controller supports smart cards with internal clocks and internal resets. It has a well defined, easy to integrate processor interface. The design has hardware support for activation, deactivation and data transfer. It also supports hardware initiated smart card deactivation on card removal.

Features

    • Supports asynchronous T = 0 and T =1 transmission protocols
    • Supports 2 –66 Mhz range for the input frequency
    • Supports class A, B and class AB smart cards
    • Timed interrupt for efficient support for synchronous protocol
    • Configurable depth for data path FIFO
    • Interrupts for all major events in hardware
    • Data filtering for signal integrity
    • C level driver for post integration SOC verification
    • Technology independent
    • Programmable timing parameters

Benefits

    • Fully synchronous
    • Technology independent
    • Functions at 2 to 66 Mhz
    • Hardware interrupts
    • Data filtering for signal integrity

Deliverables

  • Verilog RTL
  • Verification environment
  • Testcases
  • Synthesis environment/scripts
  • User manual
  • Verification guide
  • Design document

No tabs Found

UART IP

Description

The DUART is one of the tiniest UART IP Cores available on the market. The DUART is a soft core of a Universal Asynchronous Receiver/Transmitter (UART). It performs serial-to-parallel conversion on data characters received from a peripheral device or a MODEM, and parallel-to-serial conversion on data characters received from the CPU. The CPU can read the complete status of the UART at any time during the functional operation. Status information reported includes the type and condition of the transfer operations being performed by the UART, as well as any error conditions (overrun, framing). The DμART includes a programmable baud rate generator that is capable of dividing the timing reference clock input by divisors of 1 to (216-1), and producing a 16 × clock for driving the internal transmitter logic. Provisions are also included to use this 16 × clock to drive the receiver logic. The DμART has processor-interrupt system. Interrupts can be programmed to the user's requirements, minimizing the computing required to handle the communications link. The core is perfect for applications, where the UART Core and microcontroller are clocked by the same clock signal and are implemented inside the same ASIC or FPGA chip, as well as for standalone implementation, where several UARTs are required to be implemented inside a single chip, and driven by some off-chip devices.

Features

  • Majority Voting Logic
  • Adds or deletes standard asynchronous communication bits (start, stop, and parity) to or from the serial data
  • In UART mode receiver and transmitter are double buffered to eliminate the need for precise synchronization between the CPU and serial data
  • Independently controlled transmit, receive, line status, and data set interrupts
  • 16 bit programmable baud generator
  • False start bit detection
  • Line break generation and detection. Internal diagnostic capabilities:
  • Loop-back controls for communications link fault isolation
  • Overrun, framing error detection
  • Full prioritized interrupt system controls
  • Technology independent HDL Source Code
  • Fully synthesizable static design with no internal tri-state buffers

Benefits

  • D-UART

Applications

  • Serial Data communications applications
  • Modem interface
  • Embedded microprocessor boards

Deliverables

  • Source code:
  • VHDL Source Code or/and
  • VERILOG Source Code or/and
  • Encrypted, or plain text EDIF
  • VHDL & VERILOG test bench environment
  • Active-HDL automatic simulation macros
  • ModelSim automatic simulation macros
  • Tests with reference responses
  • Technical documentation
  • Installation notes
  • HDL core specification
  • Datasheet
  • Synthesis scripts
  • Example application
  • Technical support
  • IP Core implementation support
  • 3 months maintenance
  • Delivery the IP Core updates, minor and major versions changes
  • Delivery the documentation updates
  • Phone & email support
  • Tech Specs

26C92 IP

Description

The D26C92 is a Dual UART Core software compatible with the SC26C92, SCC2692 and SCN2681 with added features and deeper FIFOs. It contains: 8 character receiver, 8 character transmit FIFOs, WATCH dog timer for each receiver, mode register 0, extended baud rate, programmable receiver and transmitter interrupts. The D26C92 Dual Universal Asynchronous Receiver/Transmitter (DUART) is a communication device that provides two full-duplex asynchronous receiver/transmitter channels in a single package. It interfaces directly with microprocessors and may be used in a polled or interrupt driven system, furthermore provides modem and DMA interface. The operating mode and data format of each channel can be programmed independently. Additionally, each receiver and transmitter can select its operating speed as one of 27 fixed baud rates, a 16X clock derived from a programmable counter/timer, or an external 1X or 16X clock. The baud rate GENERATOR and counter/timer can operate directly from a crystal or from external clock inputs. The ability to independently program the operating speed of the receiver and transmitter make the UART particularlyattractive for dual-speed channel applications such as clustered terminal systems.

Features

    • Software compatible with SC26C92, SCC2692 and SCN2681 UARTs
    • Configuration capability
    • Dual full-duplex independent asynchronous receiver/transmitters
    • 8 character FIFOs for each receiver and transmitter
    • Programmable data format:
    • 5 to 8 data bits plus parity
    • ODD even, no parity or force parity
    • 1, 1.5 or 2 stop bits programmable in 1/16-bit increments
    • 16-bit programmable Counter/Timer
    • Programmable baud rate for each receiver and transmitter selectable from:
    • 27 fixed rates: 50 to 230.4k baud
    • Other baud rates to 230.4k baud at 16X
    • Programmable user-defined rates derived from a programmable counter/timer
    • External 1X or 16X clock
    • Parity, framing, and overrun error detection
    • False start bit detection
    • Line break detection and GENERATION
    • Programmable channel mode:
    • Normal (full-duplex)
    • Automatic echo
    • Local loopback
    • Remote loopback
    • Multidrop mode (also called ‘wake-up’ or ‘9-bit’)
    • Multi-function 7-bit input port:
    • Can serve as clock, modem, or control inputs
    • Change of state detection on four inputs
    • Multi-function 8-bit output port:
    • Individual bit set/reset capability
    • Outputs can be programmed to be status/interrupt signals
    • FIFO states for DMA and modem interface
    • Versatile interrupt system:
    • Single interrupt output with eight maskable interrupting conditions
    • Output port can be configured to provide a total of up to six separate wire-ORable interrupt outputs
    • Each FIFO can be programmed for four different interrupt levels
    • WATCHdog timer for each receiver
    • Maximum data transfer rates: 1X – 1Mb/sec, 16X – 1Mb/sec
    • Automatic wake-up mode for multidrop applications
    • Start-end break interrupt/status
    • Detects break which originates in the middle of a character
    • Power down mode
    • Receiver timeout mode

Benefits

    • D-26C92

Applications

    • Serial Data communications applications
    • Modem interface
    • Embedded microprocessor boards

Deliverables

  • Source code:
  • VHDL Source Code or/and
  • VERILOG Source Code or/and
  • Encrypted, or plain text EDIF
  • VHDL & VERILOG test bench environment
  • Active-HDL automatic simulation macros
  • ModelSim automatic simulation macros
  • Tests with reference responses
  • Technical documentation
  • Installation notes
  • HDL core specification
  • Datasheet
  • Synthesis scripts
  • Example application
  • Technical support
  • IP Core implementation support
  • 3 months maintenance
  • Delivery the IP Core updates, minor and major versions changes
  • Delivery the documentation updates
  • PHONE& email support

16950-UART IP

Description

The D16950 is a soft core of a Universal Asynchronous Receiver/Transmitter (UART), functionally identical to the OX16C950. It allows serial transmission in two modes: UART and FIFO. In the FIFO mode, internal FIFOs are activated, allowing 128 bytes (plus 3 bits of error data per byte in the RCVR FIFO) to be stored in both receive and transmit modes. Our efficient Core performs a serial-to-parallel conversion on data characters received from a peripheral device or a MODEM, but also parallel-to-serial conversion on data characters received from the CPU. The processor can read a complete status of the UART at any time during the functional operation. Status information reported includes the type and condition of transfer operations being performed by the UART, as well as any error conditions (parity, overrun, framing or break interrupt). The D16950 includes a programmable baud rate GENERATOR, which is capable to divide the timing reference clock input by divisors of 1 to (216-1) and produce a n × clock for driving the internal transmitter logic. Provisions are also included to use this n × clock to drive the receiver logic. We also equipped our core with a complete MODEM-control capability and a processor-interrupt system. Interrupts can be programmed in accordance to your requirements, minimizing computing required to handle the communications link. The D16950 core includes all (16450, 16550, 16650 and 16750) features and additional functions. The D16950 has ICR registers, which give additional capabilities of UART work configuration. The data transmission may be synchronized by an external clock connected to the RI (for receiver and transmitter) or the DSR (only for receiver) pin. The NMR register allows to enable a 9-bit mode transmission, with or without special character. Writing and reading from/to FIFO may be controlled by trigger level registers. Trigger level registers may be set any value from 1 to 127. In the FIFO mode, there is a selectable autoflow control feature, that can significantly reduce software overload and automatically increase the system efficiency, by controlling serial data flow, through the RTS output and the CTS input signals. The Core is perfect for applications, where the UART core and the microcontroller are clocked by the same clock signal and are implemented inside the same ASIC or FPGA chip. Nevertheless, it's also a proprietary solution for a standalone implementation, where several UARTs are required to be implemented inside a single chip and driven by some off-chip devices. Thanks to a universal interface, the D16950 core implementation and verification are very simple, just by eliminating a number of clock trees in the complete system. As all our UART Cores, the D16950 includes fully automated testbench with complete set of tests, allowing easy package validation at each stage of SoC design flow. This efficient solution is a technology independent design, that can be implemented in a variety of process technologies.

Features

    • Software compatible with 16450, 16550,16650,16750 and 16950 UARTs
    • Configuration capability
    • Separate configurable BAUD clock line
    • Majority Voting Logic
    • Two modes of operation: UART mode and FIFO mode
    • In the FIFO mode transmitter and receiver are each buffered with 128 byte FIFO to reduce the number of interrupts presented to the CPU
    • In UART mode receiver and transmitter are double buffered to eliminate a need for precise synchronization between the CPU and serial data
    • Configurable FIFO size up to 512 levels
    • Adds or deletes standard asynchronous communication bits (start, stop and parity) to or from the serial data
    • Independently controlled transmit, receive, line status and data set interrupts
    • False start bit detection
    • 16 bit programmable baud GENERATOR
    • Independent receiver clock input
    • MODEM control functions (CTS, RTS, DSR, DTR, RI, DCD)
    • Programmable Hardware Flow Control through RTS and CTS
    • Programmable Flow Control using DTR and DSR
    • Programmable in-band Flow Control using XON/XOFF
    • Programmable special characters detection
    • Trigger levels for TX and RX FIFO
    • Interrupts and automatic in-band and out-off-band flow control
    • Fully programmable serial-interface characteristics:
    • 5-, 6-, 7-, 8- or 9-bit characters
    • Even, ODD, or no-parity bit generation and detection
    • 1-, 1.5-, or 2-stop bit generation
    • Internal baud generator
    • Detection of bad data in receiver FIFO
    • Clock prescaler from 1 to 31,875
    • Enhanced isochronous clock option
    • 9- bit data mode
    • Software reset
    • Complete status reporting capabilities
    • Line break GENERATION and detection. Internal diagnostic capabilities:
    • Loop-back controls for communications link fault isolation
    • Break, parity, overrun, framing error simulation
    • Full prioritized interrupt system controls
    • Available system interface wrappers:
    • AMBA - APB Bus
    • Altera Avalon Bus
    • Xilinx OPB Bus
    • Fully synthesizable
    • Static synchronous design and no internal tri-states

Benefits

    • D-16950

Applications

    • Serial Data communications applications
    • Modem interface
    • Embedded microprocessor boards

Deliverables

  • Source code:
  • VHDL Source Code or/and
  • VERILOG Source Code or/and
  • Encrypted, or plain text EDIF
  • VHDL & VERILOG test bench environment
  • Active-HDL automatic simulation macros
  • ModelSim automatic simulation macros
  • Tests with reference responses
  • Technical documentation
  • Installation notes
  • HDL core specification
  • Datasheet
  • Synthesis scripts
  • Example application
  • Technical support
  • IP Core implementation support
  • 3 months maintenance
  • Delivery the IP Core updates, minor and major versions changes
  • Delivery the documentation updates
  • PHONE& email support

Tech Specs

SPI-Quad IP

Description

DCD’s IP Core is a technology independent design that can be implemented in a variety of process technologies. The DQSPI system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. The system can be configured as a master or a slave device. Data rates as high as CLK/2, when other vendors’ solutions offer just CLK/8. Clock control logic allows a selection of clock polarity, phase and a choice of four fundamentally different clocking protocols to accommodate most available synchronous serial peripheral devices.

When the SPI is configured as a master, software selects bit rates for the serial clock. The DQSPI automatically drive selected by SSCR (Slave Select Control Register) slave select outputs (SS7O – SS0O) and address SPI slave device to exchange serially shifted data. Error?detection logic is included to support interprocessor communications.

A write collision detector indicates when an attempt is made to write data to the serial shift register while a transfer is in progress. A multiple-master mode fault detector automatically disables DQSPI output drivers, if more than one SPI device simultaneously attempts to become bus master. The DQSPI supports two DMA modes: single transfer and multi?transfer. These modes allow DQSPI to interface to higher performance DMA units, which can interleave their transfers between CPU CYCLESor execute multi-ple byte transfers. DQSPI is fully customizable, which means it is delivered in the exact configuration to meet users’ requirements.

 

Features

    • Operates with 8, 16 and 32 bit CPUs
    • Full duplex synchronous serial data transfer
    • DMA support
    • Support for 32, 16 and 8 bit systems
    • Support for various system Bus Standards
    • Single, Dual and Quad SPI transfer
    • Multimaster system supported
    • Optional FIFO size extension (128, 256, 512B)
    • Up to 8 SPI slaves can be addressed
    • Software Slave Select Output – SSO ? selection
    • Automatic Slave Select outputs assertion during each byte transfer
    • System error detection
    • Bit rate in fast SPI Mode ½ CLK
    • Four transfer formats
    • Simple SPU and DMA interface
    • Fully synthesizable, static synchronous de-sign with no internal tri?states

Benefits

    • D-Quad-SPI

Applications

    • Embedded microprocessor boards
    • Consumer and professional audio/video
    • Home and automotive radio
    • Low-power applications
    • Communication systems
    • Digital multimeters

Deliverables

    • Source code:
    • VHDL Source Code or/and
    • VERILOG Source Code or/and
    • Encrypted, or plain text EDIF
    • VHDL & VERILOG test bench environment
    • Active-HDL automatic simulation macros
    • ModelSim automatic simulation macros
    • Tests with reference responses
    • Technical documentation
    • Installation notes
    • HDL core specification
    • Datasheet
    • Synthesis scripts
    • Example application
    • Technical support
    • IP Core implementation support
    • 3 months maintenance
    • Delivery the IP Core updates, minor and major versions changes
    • Delivery the documentation updates
    • PHONE& email support

Tech Specs

  • D-Quad-SPI

SPI-M/S IP

Description

The DSPI is a fully configurable SPI master/slave device, which allows user to configure polarity and phase of serial clock signal SCK. It allows the microcontroller to communicate with serial peripheral devices. It is also capable of interprocessor communications in a multi-master system. A serial clock line (SCK) synchronizes shifting and sampling of the information on the two independent serial data lines. DSPI data are simultaneously transmitted and received. What's the most important, it's a technology independent design that can be implemented in a variety of process technologies. The DSPI system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. It can be configured as a master or a slave device, with data rates as high as CLK/4. Clock control logic allows a selection of clock polarity and a choice of two fundamentally different clocking protocols to accommodate most available synchronous serial peripheral devices. When the SPI is configured as a master, software selects one of eight different bit rates for the serial clock. The DSPI automatically drive selected by SSCR (Slave Select Control Register) slave outputs (SS7O – SS0O) and address SPI slave device to exchange serially shifted data. What's more important, error-detection logic is included to support interprocessor communications. A write collision detector indicates, when an attempt is made, to write data to the serial shift register, while a transfer is in progress. A multiple-master mode-fault detector automatically disables DSPI output drivers, if more than one SPI devices simultaneously attempts to become bus master. What does it mean for you? The DSPI is fully customizable, which means that we deliver it tailored to your configuration and requirements. There is no need to pay extra for not used features and wasted silicon. It includes fully automated testbench with complete set of tests, allowing easy package validation at each stage of SoC design flow.

Features

    • SPI Master - 8 SPI slave select lines System error detection Mode fault error Write collision error Interrupt generation
    • Supports speeds up 1/4 of system clock Bit rates generated 1/4 - 1/512 of system clock. Four transfer formats supported Simple interface allows easy connection to microcontrollers
    • SPI Slave operation - System error detection, Interrupt generation
    • Supports speeds up 1/4 of system clock Simple interface allows easy connection to microcontrollers Four transfer formats supported
    • system interface wrappers: AMBA - APB Bus, Altera Avalon Bus, Xilinx OPB Bus
    • Fully synthesizable, Static synchronous design, Positive edge clocking and no internal tri-states Scan test ready

Deliverables

  • VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF
  • VHDL & VERILOG test bench environment Active-HDL automatic simulation macros
  • ModelSim automatic simulation macros Tests with reference responses
  • Technical documentation Installation notes HDL core specification Datasheet
  • Synthesis scripts Example application Technical support

CAN-FD Controller IP

The DCAN FD is a standalone controller for the Controller Area Network (CAN), widely used in automotive and industrial applications. It conforms to Bosch CAN 2.0B specification (2.0B Active) and CAN FD (flexible data-rate). The improved proto- col overcomes standard CAN limits: data can be transmitted faster than with 1 Mbit/s and the pay- load (data field) is up to 64 byte long and limited to 8 byte anymore. When only one node is transmit- ting, the bit-rate can be increased, because no nodes need to be synchronized. Of course, before the transmission of the ACK slot bit, the nodes  need to be re-synchronized. The core has a simple CPU interface (8/16/32 bit configurable data width), with small or big endian addressing  scheme. Hardware message filtering and 128 byte receive FIFO enable back-to-back message recep- tion, with minimum CPU load. The DCAN FD is provided as HDL source code, allowing target use  in FPGA or ASIC technologies.
Features
      • Designed in accordance to ISO 11898-1:2015
      • Supports CAN 2.0B and CAN FD frames
      • Support up to 64 bytes data frames
      • Flexible data rates supported
      • 8/16/32-bit CPU slave interface with small or big endianness
      • Simple interface allows easy connection to CPU
      • Supports both standard (11-bit identifier) and extended (29 bit identifier) frames
      • Data rate up to 8 Mbps
      • Hardware message filtering (dual/single filter)
      • 128 byte receive FIFO and transmit buffer
      • Overload frame is generated on FIFO overflow
      • Normal & Listen Only Mode
      • Transceiver Delay Compensation up to three data bit long
      • Single Shot transmission
      • Ability to abort transmission
      • Readable error counters

Deliverables

Source code

    • VHDL Source Code or/and
    • VERILOG Source Code or/and
    • FPGA Netlist

VHDL /VERILOG test bench environment

      • Active-HDL automatic simulation macros
      • NCSim automatic simulation macros
      • ModelSim automatic simulation macros
      • Tests with reference responses

Technical documentation

        • Installation notes
        • HDL core specification
        • Datasheet

Synthesis scripts

Example application

Technical support

IP Core implementation support

        • 3 months maintenance
        • Delivery of the IP Core and documentation updates, minor and major versions changes
        • Phone & email support

I2S Controller Core IP

Description

I2S Controller is a highly configurable core for use in I2S compliant CODECs. It provides a simple glueless interface to industry standard audio devices. This digital audio controller core is compliant to the dominant audio standard protocol I2S. The core is optimally architected for high performance, low latency and small silicon footprint. The core is provided with the generic processor bus interface on the system side enabling the core to be used in a variety of applications including SoC applications. The core's simple and configurable architecture is independent of implementation tools and, most importantly, target technologies. I2S core is a cost effective, end-to-end solution that allows the licensees to easily migrate to FPGA,Gate array and Standard cell technologies optimally. I2S core solution leverages years of experience in creating reusable designs for Ethernet, PCI-X, SPI-4 and Hyper Transport technologies to offer lowest risk in terms of compliance and interoperability. I2S core has been tested for Amba AHB 32-bit wide interface on the system side and DMA channel support for FIFO data transfer has also been provided in this setup. I2S Controller is a highly configurable core for use in I2S compliant CODECs. It provides a simple glueless interface to industry standard audio devices. This digital audio controller core is compliant to the dominant audio standard protocol I2S. The core is optimally architected for high performance, low latency and small silicon footprint. The core is provided with the generic processor bus interface on the system side enabling the core to be used in a variety of applications including SoC applications. The core's simple and configurable architecture is independent of implementation tools and, most importantly, target technologies. I2S core is a cost effective, end-to-end solution that allows the licensees to easily migrate to FPGA,Gate array and Standard cell technologies optimally. I2S core solution leverages years of experience in creating reusable designs for Ethernet, PCI-X, SPI-4 and Hyper Transport technologies to offer lowest risk in terms of compliance and interoperability. I2S core has been tested for Amba AHB 32-bit wide interface on the system side and DMA channel support for FIFO data transfer has also been provided in this setup.

Features

    • Compliant to I2S Serial Bus protocol
    • Supports full duplex flow control - 1 PCM playback channel and 1 record channel
    • Supports 8/16/18/20/24/32 bit DAC/ADC resolution through software configuration
    • Supports both 256 and 384 sampling frequency (fs) operating mode
    • Support 8/16/32/48/96/192/44.1/88.2/176.4 KHz audio sample frequency
    • Processor Bus 8/16/32-bit wide Interface on system side
    • Supports 1/2/4 samples per 32 bit packing option through Software configuration
    • Fully synchronous design with serial clock and system clock
    • Interrupt Support for FIFO data read/write
    • Programmable FIFO thresholds
    • Loop back mode for testing purposes

Benefits

    • Configurable Options
    • Playback and Record FIFO depths
    • Playback and Record FIFO widths
    • Processor bus width – 8/16/32
    • Synchronous and asynchronous reset

Deliverables

  • Parameterized RTL Code
  • Automated and parameterized test bench
  • Test cases
  • Synthesis environment/scripts
  • Design document
  • Acceptance Test Bench Specification (ATS)
  • Software specification

LIN Bus IP

Description

The DLIN is a soft core of the Local Interconnect Network (LIN). This interface is a serial communication protocol, designed primarily to be used in automotive applications. Compared to CAN, LIN is slower, but thanks to its simplicity, is much more cost effective. Our Core is ideal for a communication in intelligent sensors and actuators, where the bandwidth and versatility of CAN is not required. The DLIN core provides an interface between a microprocessor/microcontroller and a LIN bus. It can work as master or slave LIN node, depending on a work mode, determined by the microprocessor/microcontroller. DCD's controller supports transmission speed between 1 and 20kb/s, which allows it to transmit and receive LIN messages compatible to LIN 1.3. LIN 2.1 and the newest 2.2. The reported information status includes the type and condition of transfer operations being performed by the DLIN, as well as a wide range of LIN error conditions (overrun, framing, parity, timeout). Our Core includes programmable timer, which allows to detect timeout and synchronization error. The DLIN is described at RTL level, empowering the target use in FPGA and ASIC technologies LIN (Local Interconnect Network) is a serial communication protocol, which was created to provide a cost efficient bus communication. The LIN standard is developed by LIN consortium (More). It includes the specification of the transmission medium, the interface between development tools, the transmission protocol and the interfaces for software programming. LIN has been created to decrease costs of automotive networks and replace more expensive CAN in simple application (sensors or actuators). The LIN device can be implemented as a master or as a slave node. Transmission is initiated by Master Node, which sends the data frame to Slaves Nodes (maximum 15) throat one wire bus.

Features

    • Conforms with LIN 1.2, LIN 2.1 and LIN 2.2 specification.
    • Automatic LIN Header handling
    • Automatic Re-synchronization
    • Data rate between 1Kbit/s and 20 Kbit/s
    • Master and Slave work mode
    • Time-out detection
    • Extended error detection
    • “Break-in-data” support
    • Available system interface wrappers:
    • AMBA - APB Bus
    • Altera Avalon Bus
    • Xilinx OPB Bus

Applications

    • Automotive, industrial
    • Embedded communication systems

Deliverables

  • Source code
  • Technical support
  • Example application
  • Synthesis scripts
  • Datasheet
  • HDL core specification
  • Installation notes
  • Technical documentation
  • Tests with reference responses
  • ModelSim automatic simulation macros
  • Active-HDL automatic simulation macros
  • VHDL & VERILOG test bench environment
  • Encrypted, or plain text EDIF
  • VERILOG Source Code or/and
  • VHDL Source Code or/and

LCD/TFT Display Controller IP

HDLC Controller IP

Description

The DHDLC IP core is used for controlling HDLC/SDLC transmission frame, designed to be used with 8-bit MCU, like DP8051/DP80390. It allows to save MCU time wasted for handling HDLC/SDLC features like bit stuffing, address recognition or CRC computation. The DHDLC has implemented FIFO buffer, for both, receiver and transmitter. The DHDLC IP core is full synchronous with one clock domain design. All parameters are configurable by CPU. But there is also capability for setting parameters by modification constants in source file. There is no need to wasting silicon resources for unused features and constant settings.

Features

    • Two separate receiver and transmitter interfaces.
    • Two separate, configurable FIFO buffers for receiver and transmitter
    • Bit stuffing and unstuffing
    • Address recognition for receiver and address insertion for transmitter
    • Two or one byte address field
    • RC-16 and CRC-32 computation and checking
    • Collision detect
    • Byte alignment error detection
    • Programmable number of bits for idle detection
    • NRZI coding support
    • Shared flags, shared zeros support
    • Pad fill with flags option
    • Transmitter clock generation
    • 8-bit CPU interface
    • Interrupt output for handling control flags and FIFOs’ filling
    • Configurable core parameters

Benefits

    • D-HDLC

Applications

    • CPU based applications with serial interface based on HDLC/SDLC protocol
    • Telecommunication

Deliverables

    • Source code:
    • VHDL Source Code or/and
    • VERILOG Source Code or/and
    • Encrypted, or plain text EDIF
    • VHDL & VERILOG test bench environment
    • Active-HDL automatic simulation macros
    • ModelSim automatic simulation macros
    • Tests with reference responses
    • Technical documentation
    • Installation notes
    • HDL core specification
    • Datasheet
    • Synthesis scripts
    • Example application
    • Technical support
    • IP Core implementation support
    • 3 months maintenance
    • Delivery the IP Core updates, minor and major versions changes
    • Delivery the documentation updates
    • Phone & email support

Tech Specs

  • D-HDLC

CAN-Bus IP

Description

The DCAN is a standalone controller for the Controller Area Network (CAN), which is commonly used in automotive and industrial applications. What's most IMPORTANT, the DCAN conforms to the Bosch CAN 2.0B specification (2.0B Active). The Core has a simple CPU interface (8/16/32 bit configurable data width), with little or big endian addressing scheme. The DCAN supports both standard (11 bit identifier) and extended (29 bit identifier) frames. Hardware message filtering and 64 byte receive FIFO, enable a back-to-back message reception with a minimum CPU load. The DCAN is described at RTL level, allowing target use in FPGA or ASIC technologies. The Controller Area Network (CAN) is a advanced serial communications protocol developed by Robert Bosch GmbH. CAN protocol uses Data Link Layer and the Physical Layer in the ISO-OSI model. The CAN bus uses multi-master bus scheme with one logic bus line and equal nodes. The number of nodes is not limited by the protocol. Nodes do not have specific addresses. Instead, message identifiers are used, indicating the message content and priority of message. This also means that multicasting and broadcasting is supported by CAN. Number of nodes may be changed at run-time without disturbing the communication of the other nodes. CAN provides sophisticated error detection and error handling mechanisms and, due to differential transmission, high immunity against electromagnetic interference. Frames with errors are automatically retransmitted (except single shot transmission feature implemented in the DCAN core). Maximum data transfer rate is 1Mbps at maximum 40 m bus length when using a twisted wire pair. The bus is handled with Carrier Sense Multiple Access / Collision Detection with Non-Destructive Arbitration. This means that collision of messages is avoided by bitwise arbitration, without loss of time. CAN controller is connected to host/CPU and CAN bus transceiver, which directly connects to CAN bus line (2-wire).

Features

  • Conforms to Bosch CAN 2.0B Active
  • 8/16/32-bit CPU slave interface with little or big endianess
  • Simple interface allows easy connection to CPU
  • Data rate up to 1 Mbps
  • Hardware message filtering (dual/single filter)
  • 64 byte receive FIFO
  • One transmit buffer
  • No overload frames are generated
  • Normal & Listen Only Mode
  • Single Shot transmission
  • Ability to abort transmission
  • Readable error counters
  • Last Error Code
  • Available system interface wrappers:
    • AMBA - APB Bus
    • Altera Avalon Bus
    • Xilinx OPB Bus
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready

Benefits

 
  • D-CAN
 

Applications

  • Automotive, industrial
  • Embedded communication systems

Deliverables

    • Source code:
      • VHDL Source Code or/and
      • VERILOG Source Code or/and
      • Encrypted, or plain text EDIF
    • VHDL & VERILOG test bench environment
      • Active-HDL automatic simulation macros
      • ModelSim automatic simulation macros
      • Tests with reference responses
    • Technical documentation
      • Installation notes
      • HDL core specification
      • Datasheet
    • Synthesis scripts
    • Example application
    • Technical support
      • IP Core implementation support
      • 3 months maintenance
      • Delivery the IP Core updates, minor and major versions changes
      • Delivery the documentation updates
      • Phone & email support

Tech Specs

  • D-CAN

I2C Controller IP

Description

The I2C Controller IP is compact low power and scalable IP core. I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices. It is most suitable for applications requiring communication over short distance between many devices. The standard VCI interface provided in I2C IP core makes integration easy into any design.I2C controller IP core is fully synthesizable core suitable for different process. The IP core is portable to an ASIC or a FPGA. It has been validated on Xilinx platform. Along with the IP core, we will provide complete test environment with constraint randomized test cases and our full support during integration.

Features

    • Compliant to version 2.1 of the I2C Bus standard
    • System Bus Interface - VCI
    • Optional Bus Interface - AHB, APB, OCP
    • Data transfers up to 400 Kbps
    • Supports Master Transmitter Mode - Serial data output on SDA and clock on SCL output
    • Supports Master Receiver Mode - Serial data is received via SDA while SCL outputs the serial clock
    • Single master mode
    • Supports up to eight slave devices with unique address

Benefits

    • I2C Controller

Applications

    • I2C Controller

Deliverables

    • Verilog source / encrypted code of the IP core
    • Verilog Test environment and test scripts
    • Synthesis constraints and scripts
    • Documentation – Design , Verification & Integration guide
    • FPGA validation platform (Xilinx / Altera

Tech Specs

Host Interface

    • The host interface is a 32 bit VCI slave interface. This interface is used to integrate the IP core within the SoC design and to read/ write the internal registers of the core.

Control and Status Registers

    • This block consists of I2C registers for data transfer and control and status information. These registers are programmable through VCI interface.

Clock Generator

    • This functional block controls the generation of I2C clock from the IP core for data transfer.

Command Control

    • This block consists of state machines for sending command and data bytes on to the I2C bus.

Transmit and Receive

  • This block has the buffers and the control logic for transmitting and receiving the data through host and I2C interfaces.

I2C IP

Description

The I2C is a two-wire, bi-directional serial bus, which provides a simple and efficient method of short distance data transmission between many devices. The DI2CMS core provides an interface between a microprocessor/microcontroller and an I2C bus. It can work as a master or a slave transmitter/receiver - depending on a working mode, determined by the microprocessor/microcontroller. The DI2CMS coreincorporates all features required by the latest I2C specification, including clock synchronization, arbitration, multi-master systems and a high-speed transmission mode (the DI2CMS supports all the transmission speed modes).Built-in timer allows operation from a wide range of the clk frequencies. The DI2CMS is technology independent, that's why a VHDL or VERILOG design can be implemented in a variety of process technologies. Furthermore, it can be also completely customized in accordance to the customer's needs. The DI2CMS is delivered with fully automated testbench and complete set of tests, allowing easy package validation at each stage of SoC design flow. The I2C-bus supports any IC fabrication process (NMOS, CMOS, bipolar). Two wires, serial data (SDA) and serial clock (SCL), carry information between devices connected to the bus. Each devices is recognised by a unique address – whether it is a microcontroller, LCD driver, memory or keyboard interface. It can operate as either transmitter or receiver, depending on the function of the device. Obviously an LCD driver is only a receiver, whereas a memory can both receive and transmit data. In addition to transmitters and receivers, devices can also be considered as masters or slaves when performing data transfers (see Figures below). A master is the device which initiates a data transfer on the bus and generates the SCL clock signals. A slave is the device addressed by a master. The I2C-bus is a multi-master bus. This means that more than one device capable of controlling the bus can be connected to it. As masters are usually microcontrollers or microprocessors. i2c-ms

Features

    • Conforms to v.3.0 of the I2C specification
    • Master mode
    • Master operation
    • Master transmitter
    • Master receiver
    • Support for all transmission speeds
    • Standard (up to 100 kb/s)
    • Fast (up to 400 kb/s)
    • Fast Plus (up to 1 Mb/s)
    • High Speed (up to 3,4 Mb/s)
    • Arbitration and clock synchronization
    • Support for multi-master systems
    • Support for both 7-bit and 10-bit addressing formats on the I2C bus
    • Build-in 8-bit timer for data transfers speed adjusting
    • Slave mode
    • Slave operation
    • Slave transmitter
    • Slave receiver
    • Supports 3 transmission speed modes
    • Standard (up to 100 kb/s)
    • Fast (up to 400 kb/s)
    • Fast Plus (up to 1 Mb/s)
    • High Speed (up to 3,4 Mb/s)
    • Allows operation from a wide range of input clock frequencies
    • User-defined data setup time
    • User-defined timing (data setup, start setup, start hold, etc.)
    • Simple interface allows easy connection to microprocessor/microcontroller devices
    • Interrupt generation
    • Available system interface wrappers:
    • AMBA - APB Bus
    • Altera Avalon Bus
    • Xilinx OPB Bus
    • Fully synthesizable
    • Static synchronous design
    • Positive edge clocking and no internal tri-states
    • Scan test ready

Benefits

    • D-I2C-MS

Applications

    • Embedded microprocessor boards
    • Consumer and professional audio/video
    • Home and automotive radio
    • Low-power applications
    • Communication systems
    • Cost-effective reliable automotive systems

Deliverables

  • Source code:
  • VHDL Source Code or/and
  • VERILOG Source Code or/and
  • Encrypted, or plain text EDIF
  • VHDL & VERILOG test bench environment
  • Active-HDL automatic simulation macros
  • ModelSim automatic simulation macros
  • Tests with reference responses
  • Technical documentation
  • Installation notes
  • HDL core specification
  • Datasheet
  • Synthesis scripts
  • Example application
  • Technical suppor
  • IP Core implementation support
  • 3 months maintenance
  • Delivery the IP Core updates, minor and major versions changes
  • Delivery the documentation updates
  • Phone & email support