The DCAN is a standalone controller for the Controller Area Network (CAN), which is commonly used in automotive and industrial applications. What's most IMPORTANT, the DCAN conforms to the Bosch CAN 2.0B specification (2.0B Active). The Core has a simple CPU interface (8/16/32 bit configurable data width), with little or big endian addressing scheme. The DCAN supports both standard (11 bit identifier) and extended (29 bit identifier) frames. Hardware message filtering and 64 byte receive FIFO, enable a back-to-back message reception with a minimum CPU load. The DCAN is described at RTL level, allowing target use in FPGA or ASIC technologies.
The Controller Area Network (CAN) is a advanced serial communications protocol developed by Robert Bosch GmbH. CAN protocol uses Data Link Layer and the Physical Layer in the ISO-OSI model. The CAN bus uses multi-master bus scheme with one logic bus line and equal nodes. The number of nodes is not limited by the protocol.
Nodes do not have specific addresses. Instead, message identifiers are used, indicating the message content and priority of message. This also means that multicasting and broadcasting is supported by CAN.
Number of nodes may be changed at run-time without disturbing the communication of the other nodes.
CAN provides sophisticated error detection and error handling mechanisms and, due to differential transmission, high immunity against electromagnetic interference. Frames with errors are automatically retransmitted (except single shot transmission feature implemented in the DCAN core). Maximum data transfer rate is 1Mbps at maximum 40 m bus length when using a twisted wire pair.
The bus is handled with Carrier Sense Multiple Access / Collision Detection with Non-Destructive Arbitration. This means that collision of messages is avoided by bitwise arbitration, without loss of time.
CAN controller is connected to host/CPU and CAN bus transceiver, which directly connects to CAN bus line (2-wire).
- Conforms to Bosch CAN 2.0B Active
- 8/16/32-bit CPU slave interface with little or big endianess
- Simple interface allows easy connection to CPU
- Data rate up to 1 Mbps
- Hardware message filtering (dual/single filter)
- 64 byte receive FIFO
- One transmit buffer
- No overload frames are generated
- Normal & Listen Only Mode
- Single Shot transmission
- Ability to abort transmission
- Readable error counters
- Last Error Code
- Available system interface wrappers:
- AMBA - APB Bus
- Altera Avalon Bus
- Xilinx OPB Bus
- Fully synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready
- Automotive, industrial
- Embedded communication systems
- Source code:
- VHDL Source Code or/and
- VERILOG Source Code or/and
- Encrypted, or plain text EDIF
- VHDL & VERILOG test bench environment
- Active-HDL automatic simulation macros
- ModelSim automatic simulation macros
- Tests with reference responses
- Technical documentation
- Installation notes
- HDL core specification
- Synthesis scripts
- Example application
- Technical support
- IP Core implementation support
- 3 months maintenance
- Delivery the IP Core updates, minor and major versions changes
- Delivery the documentation updates
- Phone & email support