8259-Interupt Controller IP

Description

The D8259 is a soft Core of Programmable Interrupt Controller. It is fully compatible with the 82C59A device. Our efficient IP core can manage up to 8-vectored priority interrupts for the processor. Moreover, you can also program it to cascade and gain up to 64 vectored interrupts. And if it's not enough, you can always get more than 64 vectored interrupts. Just program our IP Core to the Poll Command Mode. The D8259 can operate in all 82C59A modes and it supports all 82C59A features. The D8259 Package includes fully automated testbench. Thanks to complete set of tests, you can easily validate the whole package at each stage of SoC design flow.

Features

    • 8 vectored priority interrupts
    • Up to sixty-four vectored priority interrupts with cascading
    • Support for all 82C59A modes features
    • MCS-80/85 and 8088/8086 processor modes
    • Fully nested mode and special fully nested mode
    • Special mask mode
    • Buffered mode
    • Pool command mode
    • Cascade mode with master or slave selection
    • Automatic end-of-interrupt mode
    • Specific and non-specific end-of-interrupt commands
    • Automatic and Specific Rotation
    • Edge and level triggered interrupt input modes
    • Reading of interrupt request register (IIR) and in-service register (ISR) through data bus
    • Fully synthesizable HDL Source Code
    • Static design and no internal tri-states

Applications

    • Embedded microprocessor boards

Deliverables

  • VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF
  • VHDL & VERILOG test bench environment Active-HDL automatic simulation macros
  • ModelSim automatic simulation macros Tests with reference responses
  • Technical documentation Installation notes HDL core specification Datasheet
  • Synthesis scripts Example application Technical support

SLIC IP

LVDS TX PHY IP

Description

This is a physical layer for LVDS TX. It consists of six differential channels and supports 167.86 Mbps to 1.25Gbps data rate.

Features

    • LVDS Tx compliant with EIA/TIA-644 LVDS
    • Up to 1.25Gbps/lane data rate
    • 3.3V/1.2V power supply
    • Configurable common mode voltage
    • Supports reduced swing mode
    • Supports loop back test mode
    • Supports metal option TBD
    • Used devices - Core voltage RVT-NMOS/PMOS, Diode, 3.3V OD-NMOS/PMOS, Diode, NMOS cap, BJT, Un-silicided poly resister

Deliverables

  • Datasheet
  • Integration guideline
  • GDSII or Phantom GDSII
  • Layer map table
  • CDL netlist for LVS
  • LEF
  • Verilog behavior model
  • Liberty timing model
  • DRC/LVS/ERC results

The DEEPROM performs communication and exchanges data between external serial EEPROM Memory and CPU’s RAM memory interface.

EEPROM Controller IP

The DEEPROM performs communication and exchanges data between external serial EEPROM Memory and CPU’s RAM memory interface.

SMART Card Interface IP

Smart Card Controller IP

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CAN-Bus IP

Description

The DCAN is a standalone controller for the Controller Area Network (CAN), which is commonly used in automotive and industrial applications. What's most IMPORTANT, the DCAN conforms to the Bosch CAN 2.0B specification (2.0B Active). The Core has a simple CPU interface (8/16/32 bit configurable data width), with little or big endian addressing scheme. The DCAN supports both standard (11 bit identifier) and extended (29 bit identifier) frames. Hardware message filtering and 64 byte receive FIFO, enable a back-to-back message reception with a minimum CPU load. The DCAN is described at RTL level, allowing target use in FPGA or ASIC technologies. The Controller Area Network (CAN) is a advanced serial communications protocol developed by Robert Bosch GmbH. CAN protocol uses Data Link Layer and the Physical Layer in the ISO-OSI model. The CAN bus uses multi-master bus scheme with one logic bus line and equal nodes. The number of nodes is not limited by the protocol. Nodes do not have specific addresses. Instead, message identifiers are used, indicating the message content and priority of message. This also means that multicasting and broadcasting is supported by CAN. Number of nodes may be changed at run-time without disturbing the communication of the other nodes. CAN provides sophisticated error detection and error handling mechanisms and, due to differential transmission, high immunity against electromagnetic interference. Frames with errors are automatically retransmitted (except single shot transmission feature implemented in the DCAN core). Maximum data transfer rate is 1Mbps at maximum 40 m bus length when using a twisted wire pair. The bus is handled with Carrier Sense Multiple Access / Collision Detection with Non-Destructive Arbitration. This means that collision of messages is avoided by bitwise arbitration, without loss of time. CAN controller is connected to host/CPU and CAN bus transceiver, which directly connects to CAN bus line (2-wire).

Features

  • Conforms to Bosch CAN 2.0B Active
  • 8/16/32-bit CPU slave interface with little or big endianess
  • Simple interface allows easy connection to CPU
  • Data rate up to 1 Mbps
  • Hardware message filtering (dual/single filter)
  • 64 byte receive FIFO
  • One transmit buffer
  • No overload frames are generated
  • Normal & Listen Only Mode
  • Single Shot transmission
  • Ability to abort transmission
  • Readable error counters
  • Last Error Code
  • Available system interface wrappers:
    • AMBA - APB Bus
    • Altera Avalon Bus
    • Xilinx OPB Bus
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready

Benefits

 
  • D-CAN
 

Applications

  • Automotive, industrial
  • Embedded communication systems

Deliverables

    • Source code:
      • VHDL Source Code or/and
      • VERILOG Source Code or/and
      • Encrypted, or plain text EDIF
    • VHDL & VERILOG test bench environment
      • Active-HDL automatic simulation macros
      • ModelSim automatic simulation macros
      • Tests with reference responses
    • Technical documentation
      • Installation notes
      • HDL core specification
      • Datasheet
    • Synthesis scripts
    • Example application
    • Technical support
      • IP Core implementation support
      • 3 months maintenance
      • Delivery the IP Core updates, minor and major versions changes
      • Delivery the documentation updates
      • Phone & email support

Tech Specs

  • D-CAN

I2C Controller IP

I2C IP