USB3.0 PCIe3 SATA3 Combo PHY IP

Description

The MiPHYA c4.0 macrocell is extracted from production chips, it implements the lower (physical) layer protocols of the following standards:
  • USB 3.0 SuperSpeed
  • PCI-e 3.0
  • SATA gen1/2/3
Data transmission and reception are provided over a dual differential pair CABLE. The TX (transmit) and RX (receive) serial channels operate plesiochronously (NRZ). The macro-cell can be used in Host or Device applications.

Features

    • Serial transceiver (physical layer)
    • Serializer and deserializer
    • Direct support for USB3.0 SuperSpeed at 5.0 Gbit/s
    • Direct support for 6.0 Gbit/s SATA
    • 2.5 and 5.0 Gbit/s PCI Express operation
    • Embedded oscillator
    • High-performance PLL
    • 20-bit parallel interface
    • SSC modulation
    • Comma detect to provide word alignment of incoming serial stream
    • Requires DC-balanced encoding scheme
    • Integrated impedance adaptation to transmission line characteristics
    • Serial TX buffer with programmabl amplitude, pre-emphasis and slew rate
    • OOB signaling
    • JTAG test access port allows Internal loop-back for self-test
    • Random pattern auto-test
    • 1.1 V power supply -5 / +10%
    • 1.8 or 2.5 V power supply +/- 10%
Integrated BIST allows:
    • Self test of the macrocell in loop back mode at Gigabit rate on production testers
    • Self test of the macrocell at system level, either in internal/external loop back mode or between different chips in transmission mode

Applications

    • USB 3.0 SuperSpeed
    • PCI-e 3.0
    • SATA gen1/2/3 Transmission schemes encoding octets a 10-bit code groups to form a DC-balanced stream
    • High-performance backplane interconnect

Deliverables

  • GDSII layout and layer map files with Abstract with size and pin locations (lef)
  • Verilog-a, CDL, encrypted Spectra netlist with Verification reports and environment Test cases, bring-up plans, coverage Re- ports
  • System level simulation model for channel simulations

USB 2.0 Super Speed host Controller IP

USB 2.0 Audio Design Platform IP

Description

    • The USB 2.0 Audio Design platform is a complete ,integrated solution,designed to be used in USB based Audio Devices such as speaker and microphones. You can use it in various applications,like portable flash memories, digital audio players, card readers and digital cameras.
This includes :
  • DUSB2 peripheral controller designed to support 12 Mb/S full speed and 480 Mb/S high speed serial data transmission rates.
  • DP8051XP ultra high performance ,speed optimized fully customizable 8051 8 bit microcontroller with built in debug IP core.
  • Audio device stack optimized software for DP8051XP 8bit CPU.
  • FPGA board with ready to use , pre programmed example USB stereo speakers applications.
  • Supports UTMI Transceiver Macrocell interface.

Features

    • Full complience with the USB 2.0 specifications
    • Full speed 12 Mbps operation
    • High speed 480 Mbps operation
    • Suspend and resume power management functions
    • 100% software compatible with 8051 industry standard
    • Upto 256 bytes of internal data memory
    • Up to 64k bytes of internal or external program Memory
    • User programmable program memory wait states solution for wide range of memories speed
    • User programmable External data memory wait state solution for wide range of memories speed
    • Fully syntheziable, static synchronous design with positive edge clocking and no internal tri states
    • Scan test ready

      Benefits

    • Fully Certified
    • Shipped in millions of products
    • Supper Low Power Consumption

Deliverables

  • Verilog/Vhdl Source Code
  • Modelsim automatic simulation macros
  • Audio device software stack source code
  • FPGA board with ready to use preprogrammed example application
  • Synthesis script
  • DataSheet

USB 3.1 PHY IP

Description

T2M a leading provider of High Speed Serial Interface IPs solutions, provides 10Gbps SerDes in leading 28nm process which supports USB 3.1 PMA specification. The transceiver is integrated with low jitter 10GHz PLL which offers excellent phase noise margin. This IP also supports 5 Gbps USB 3.0 standard.
Technology Option
  • GF 28SLP
  • TSMC 65G
  • TSMC 28HPC (0.9V)
Power Management
  • 4 Defined Power States
  • Active Current Sensing
  • Maximum Power Level Enumeration

Features

  • USB 3.1 with backward compatibility (USB 3.0) Meeting all specs of USB 3.1
  • Parallel data width 8 Bits with QUAD configuration ( 4 TX and 4RX ), Single Lane Configuration (1 Tx, 1Rx)
  • Support Signal loss & receiver detection
  • Programmable 3 tap & de-emphasis, Support 1m cable
  • Optimized Metal Stakes for Lower NRE expense ( 6020+LB )
  • 1.0V supply to support -40 to 125 deg.C
  • CDR logic for better data alignment and locking, Complaint with PIPE 4.2
  • High speed low jitter 10GHz PLL
  • Applications

  • Storage
  • Switches and Bridge
  • Surveillance Camera
  • Digital Still Camera
  • 4K/8K TV

    Deliverables

  • GDSII layout and layer map files with Abstract with size and pin locations (lef)
  • verilog-a, CDL, encrypted Spectra netlist and Verification reports and environment
  • Test cases, bring-up plans, coverage Reports , Timing views (.lib)
  • Synthesis environment/Scripts , System level simulation model for channel simulations

USB 3.0 Host controller IP