Wireless Connectivity IP

ZigBee SoC White Box IP

Description

A low-power, highly-integrated SoC solution, the Zigbee chip is a true 2.4GHz SoC solution with Zigbee compliant platform and supports IEEE 802.15.4 Standard. Combined with the Zigbee stack, the solution can be used for a wide range of applications and is perfect for creating interoperable solution for home or office usage.

The chip is designed to offer high integration, ultra-low power application capabilities. It integrates strong 32-bit MCU, 2.4G Radio, 16KB SRAM, 128/256/512KB external FLASH or 512KB internal Flash, 14bit ADC with PGA, 6-channel PWM, three quadrature decoders, a hardware keyboard scanner (Keyscan), abundant GPIO interfaces, multi-stage power management module and nearly all the peripherals needed to construct a powerful wireless Zigbee/IEEE 802.15.4 system.

With the high integration level, few external components are needed to satisfy customers’ ultra-low cost requirements.

Features

    • Embed 32-bit high performance MCU with clock up to 48MHz
    • external 128/256/512KB FLASH or internal 512KB Flash
    • Data memory: 16KB on-chip SRAM
    • 12MHz/16MHz Crystal and 32KHz/32MHz embedded RC oscillator

A rich set of I/Os:

    • Up to 35/37/21 GPIOs depending on package option
    • SPI, I2C, UART, USB, Debug Interface Up to 6 channels of PWM

Sensor:

      • 14bit ADC with PGA;
      • Temperature sensor
      • Three quadrature decoders
      • Embeds hardware AES
      • Compatible with USB2.0 Full speed mode
      • Operating temperature: -40~+85 industrial temperature range
      • 2.4GHz RF transceiver embedded
      • Embeds internal RF matching circuit
      • RF link data rate: 250Kbps as specified in 802.15.4
      • Sensitivity: typical value -98dBm
      • Tx output power up to +8dBm
      • Single-pin antenna interface
      • RSSI monitoring

Benefits

    • Supports Zigbee Pro feature set
    • Thread support
    • Compliant with: Zigbee Home Automation, Zigbee Light Link, Zigbee Human Interface, and Zigbee RF4CE profiles
    • A range of reference applications for RF4CE remote controls and ZLL lighting systems to enable fast product development

Applications

    • Smart Home
    • Smart Lighting
    • Home/Building Automation
    • Smart Grid
    • Intelligent Logistics/Transportation/City
    • Consumer Electronics
    • Industrial Control
    • Health Care

Deliverables

  • RTL source code
  • SW source code
  • Technical Documents, and integration support
  • Reference code for Zigbee stack
  • Reference design, and SDK

ZigBee Sub1 Ghz 802.15.4 RF IP

Description

This IP is a fully integrated system-on-chip radio transceiver targeting Smart Grid applications. The performance is tailored for extremely low power operation to be used in sensor monitoring networks and remote control for wireless networks. Transmitter output power ranges from -8 to +15 dBm, while receiver sensitivity is -110 dBm at 25kbps data rate. Additional peripherals such as ADC, SPI, I2C, UART, I2S and timers are all included on the same chip, resulting in a compact system solution.This is ideal for portable applications in frequency ranges 863-928 MHz , in particular those needing long battery life and/or signal processing, such as AMR, WSN and medical.

Features

    • Ultra-low power 863-928 MHz transceiver
    • Low voltage operation from 3.6 V down to 1.0? V
    • Minimum current standby mode with RTC based on 32 ?kiHz crystal oscillator: 1? µA at 37?°C
    • Low continuous Rx current: 3.5 mA (1 ?V)
    • RF data rate up to 400 kb/s
    • Rx sensitivity -110 dBm at 25 kb/s in FSK modulation, -115 dBm at 2 kb/s in OOK modulation
    • Digital RSSI: 3 dB/step from noise level up to -30 dBm
    • Flexible modulation: FSK, OOK, 2-FSK, 4-FSK, QPSK
    • 16/32-bit DSP/CPU, 120 µA/MHz, dual MAC
    • Software development kit: gcc, gdb, ISS, Eclipse
    • 96 kiB low leakage SRAM (program and data)
    • Integrated ADC (10 kS/s), power management, LED current sources
    • Standard digital interfaces: SPI, UART, I2C, I2S and GPIO
    • ETSI EN300-220 V2.2.2 and FCC part 15.247 and 15.249 compliant

Applications

    • Automatic Meter Reading (AMR)
    • Wireless Sensor Networks (WSN)
    • Medical and Body Area Networks (BAN)
    • Home automation

Deliverables

  • Samples and evaluation kits are available
  • Packaging options: bare die or QFN
  • Derivatives custom requirements

ZigBee Transceiver PHY IP

Description

The modulation and spreading functions for the O-QPSK PHYs are processed through 3 steps. First, each 4 bits are gathered to represent 1 symbol which has a value from 0 to 15. Second, each symbol is used to select among 16 PN sequences called chip. Finally, each chip is modulated using O-QPSK with half-sine pulse shaping. Once a preamble is detected, the Start of Frame Delimiter (SFD), frame length, and other receiver status information is sent to the upper layer. Additionally, the payload data is written to the received data buffer to create the PSDU packet, which is transferred to the MAC layer when requested. The PHY notifies the MAC layer for arrival of MAC Protocol Data Unit (MPDU) along with the LQI information via an interrupt. If a valid preamble is not detected, it gives feedback to the packet time error detection block to restart the energy detection process. The design includes ED and LQI circuits to support CCA modes by MAC defined in IEEE 802.15.4. The design includes a standard 32-bit AHB-lite, slave interface version 3.0, with registers as defined in the Register Description section of the Datasheet.

Features

    • Low power transceiver PHY IP for ZigBee applications, compliant with IEEE 802.15.4 standard.
    • Efficient demodulator with frame synchronization and frequency offset compensation.
    • Supports 2 MHz IF input (reconfigurable on request).
    • Offset-QPSK (OQPSK)
    • Chip rate: 2000 kchips/sec
    • Bit rate: 250 kbits/sec
    • Symbol rate: 62.5 ksymbols/sec
    • Spreading sequence: 16-ary orthogonal
    • Support a carrier frequency offset (CFO) up to 250 KHz
    • Sampling frequency: 8 MHz (reconfigurable on request)
    • Uses single-bit limiter (8-bit ADC version available on request)
    • AHB-Lite bus interface (other interfaces available on request)

Applications

    • Home automation
    • Health care
    • Smart energy
    • Smart metering Utility Network (SUN)

Deliverables

  • Synthesizable Verilog
  • System Model (Matlab) and documentation
  • Verilog Test Benches
  • Documentation

DVB S2/S Satellite Tuner SoC White Box IP

Description

This satellite tuner is a direct-conversion (zero IF) receiver for digital TV Broadcasting. On the RF input, there is a variable gain, low-noise amplifier (VGLNA). The RF gain is monitored by an automatic gain control (AGC) circuit to ensure an optimal signal level for the two mixers. Each mixer, which down-converts the signal to the baseband, is followed by an AGCcontrolled VGA, a low-pass filter and a second VGA. The local oscillator (LO) signals are provided by an integrated fractional-N phase locked loop (PLL), which contains an on-chip voltage-controlled oscillator (VCO) meeting stringent phase noise requirements.

The PLL loop filter is partly integrated. The LO frequencies are programmable between 950 MHz and 2150 MHz. The comparison frequency for the phase-frequency detector (PFD) is generated by dividing the crystal oscillator reference frequency. The crystal frequency may be within the range 15 MHz to 31 MHz depending on the application.

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Features

    • High volume production proven in leading STBs
    • RF-to-Baseband direct conversion architecture
    • Single 3.3-V DC supply, low consumption
    • Outstanding performance in heavily loaded spectrum conditions
    • Input frequency range: 950 to 2150 MHz
    • Supports 1 to 60 Msymb/s using internal filter
    • Specific operating mode for symbol rates up to 220 Msymb/s
    • RF-AGC or channel-AGC support
    • Extremely low-phase noise, compliant with DVB-S2 requirements using fractional-N Synthesizer
    • Low external component count
    • Flexible crystal frequency output to drive the demodulator and/or other tuner ICs
    • Continuously variable gain
    • Programmable 6 to 50 MHz cut-off frequency (Butterworth 5th-order baseband filters)
    • Compatible with 5-V and 3.3-V I2C bus

Applications

    • Direct broadcasting satellite (DBS), satellite modems: BPSK, QPSK, 8PSK, 16/32 APSK modulations
    • Input frequency range: 950 to 2150 MHz
    • Extremely low-phase noise, compliant with DVB-S1 and DVB-S2
    • Set-top boxes, PCTV and iDTV
    • Outdoor units

Deliverables

  • White Box IP – source Code delivery
  • RTL source code
  • Software source code
  • Technical documents
  • Test vectors and simulation model
  • Host emulation test environment
  • Porting & Integration support

DVB T/C Demodulator SoC White Box IP

Description

The V0367 inherits the functionality of the industry-leading enhanced V0362 terrestrial and V0297E cable demodulators in one single advanced combo receiver.

The V0367 COFDM section of the receiver is fully compliant with the DVB-T standard framing structure, channel coding and modulation. The symbol, timing and carrier recovery loops are completely digital and tailored to comply with state-of-the-art RF down-converting tuner devices.

The V0367 DVB-C section is a complete QAM (quadrature amplitude modulation) demodulation and FEC (forward error correction) solution that performs IF-to-transport stream block processing of QAM signals.

The demodulator provides error-corrected MPEG transport-stream outputs which can be routed to the transport sub-system.

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Features

Combined DVB-T/-C receiver

    • DVB-T demodulation
    • DVB-C demodulation
    • I²C serial bus interface
    • Compatible with low- to high-IF tuners
    • Flexible clock management
    • ADC for RF signal strength indicator
    • Flexible and DVB-CI compliant TS output
    • Ultra-compact TQFP64 package

Benefits

    • This highly integrated SoC helps to reduce board area and manufacturing cost, allowing low cost and small size STBs to be designed for either DVB-C or DVB-T networks.
    • Flexible AGC for different signal environments.
    • Best-in-class, low-power standby mode, to meet emerging energy standards for STBs.
    • Clock-rate management and improvements in channel acquisition efficiency enable a powerefficient standby mode.
    • Enables fast and seamless integration in complex digital TV systems such as iDTV, set-top boxes or PCTV dongles.

Deliverables

  • Verilog Source RTL Code plus Simulation Environment
  • Verification Environment
  • Integration support
  • Datasheet/Integration Guide/Verification Guide

DVB S2X/T2/C Demod+H264 STB SoC White Box IP

Description

The device integrates leading ARM® application processors architecture and GPU to provide thin client platforms, or interactive broadcast set top-box (STB) platforms, supporting the latest middleware and software solutions.

The device’s integrated carrier-grade fully-offloaded Wi-Fi MAC allows full HD video streaming throughout the home, making it the ideal device for Wi-Fi client boxes.

The device supports full HD, high-efficiency video coding (HEVC) reducing memory bandwidth for video distribution.

Features

    • Multi-core ARM® Cortex™ application CPU delivering up to 6000 DMIPS
    • High-performance GPU for fluid 3D graphics (ARM® Mali™-400)
    • DDR3/3L 32-bit interface running at up to 1066 MHz (DDR3-2133)
    • HEVC Main10 @ L4.1 (1080p60)
    • H.264 AVC, @ L4.2 (1080p60)
    • H.264 MVC and SHP @ L4.1 (1080p30L30R)
    • VC-1, MPEG4, MPEG2, AVS, AVS+
    • Web-based content decoding: Flash, DivX, Xvid, MJPEG, WMV
    • High-quality Faroudja video post-processing, including support for Blu-ray HDR10 content
    • HDMI-TX 1.4b/2.0a @ 1080p60 with HDCP 1.4 and 2.2
    • Supporting 802.11.a/b/g/n/ac wave 2
    • Up to 4 x 4 MIMO
    • Supports single-band 5 GHz or 2.4 GHz, or dual-band switchable
    • Generation 4 security for concurrent CA/DRM support, including schemes such as NSK 2.1, SVP, DTCP-IP, PlayReady, DVB-CPCM, DivX and Marlin
    • 1 x USB 2.0
    • 1 x USB 3.0
    • 1 x SD card
    • 1 x eMMC
    • 1 x Smartcard
    • 1 x Ethernet GMAC/RGMII
    • 4 x Input transport streams

Application

    • IP Client & Broadcast Platform - UHD 4Kp60
    • Server and Client Platform - UHD 60 fps
    • HEVC IP Client, Satellite or Cable Server - Dual HD/4K
    • Broadcast HD, HEVC, S2X/C/I

Deliverables

  • Verilog Source RTL Code plus Simulation Environment
  • C Source Code
  • Physical Design scripts - Synopsys synthesis
  • Hardware simulation test bench with regression test suit
  • Reference platform drivers

DVB S2X Satellite Full Band Capture Tuner Demodulator SoC White Box IP

Description

The iD135 has been designed for Satellite Broadband applications, leveraging Ka-band and multi-spot beam technology carried by the latest high-throughput satellites (HTSs).

The iD135 has been designed to enable single-carrier usage of HTS transponders. The device implements two high-symbol-rate (HSR) demodulators compliant with Annex M of the DVB-S2/S2X specification EN 302 307, and provides full HW support for network clock recovery (NCR) in order to enable external return-channel modulators.

The iD135 may be used in standard broadcast environments as an 8-channel DVB-S2/S2X receiver enabling multi-channel distribution and/or fast channel change scenarios.

Features

Two high-symbol-rate (HSR) demodulators:

  • Maximum baud rate 500 Msymbol/s
  • Up to two slices each
  • DVB-S2/S2X and Annex M compliant
  • Up to 8 multi-standard demodulators:
  • S/S2/S2X/DTV
  • Integrated full-band tuners and ADCs
  • High-speed digital multiplexer to connect any tuner to any demodulator
  • NCR PLL support

Flexible transport stream processor:

  • PID filtering, PCR re-stamping and re-labelling, GSE label filtering
  • TS merger (multiplex)
  • Channel bonding
  • Low power consumption
  • Wake-on-network PID or GSE label
  • Fast auto scan
  • Signal monitoring, spectral analysis, bit error rate test and reporting

Interfaces:

  • Crystal oscillator
  • I2C serial bus interface, including private repeater for optional LNA
  • TS, 8 serial, 2 parallel or multiplexed
  • JTAG for boundary scan
  • DiSEqC 1.x and DiSEqC2.x compatible receiver, 22-kHz
  • FSK modem
  • Flexible GPIOs and interrupts

Technology:

  • Single rail supply with inbuilt SMPSs for internal supply generation
  • Fine-grained power management
  • VQFPN-mr 13x13 mm2 package, RoHS
  • Temperature range -40 to +85 °C ambient

Applications

  • Verilog Source RTL Code plus Simulation Environment
  • Technical Documents

Deliverables

  • Verilog Source RTL Code plus Simulation Environment
  • C Source Code
  • Physical Design scripts - Synopsys synthesis
  • Hardware simulation test bench with regression test suit
  • Reference platform drivers

Highly-integrated SoC solution, the Zigbee chip is a true 2.4GHz SoC solution.

Bluetooth Dual Mode v4.2 RF Transceiver IP

Description

A low-power, highly-integrated SoC solution, the Zigbee chip is a true 2.4GHz SoC solution with Zigbee compliant platform and supports IEEE 802.15.4 Standard. Combined with the Zigbee stack, the solution can be used for a wide range of applications and is perfect for creating interoperable solution for home or office usage.

The chip is designed to offer high integration, ultra-low power application capabilities. It integrates strong 32-bit MCU, 2.4G Radio, 16KB SRAM, 128/256/512KB external FLASH or 512KB internal Flash, 14bit ADC with PGA, 6-channel PWM, three quadrature decoders, a hardware keyboard scanner (Keyscan), abundant GPIO interfaces, multi-stage power management module and nearly all the peripherals needed to construct a powerful wireless Zigbee/IEEE 802.15.4 system.

With the high integration level, few external components are needed to satisfy customers’ ultra-low cost requirements.

Features

    • Embed 32-bit high performance MCU with clock up to 48MHz
    • external 128/256/512KB FLASH or internal 512KB Flash
    • Data memory: 16KB on-chip SRAM
    • 12MHz/16MHz Crystal and 32KHz/32MHz embedded RC oscillator

A rich set of I/Os:

    • Up to 35/37/21 GPIOs depending on package option
    • SPI, I2C, UART, USB, Debug Interface
    • Up to 6 channels of PWM

Sensor

    • 14bit ADC with PGA;
    • Temperature sensor
    • Three quadrature decoders
    • Embeds hardware AES
    • Compatible with USB2.0 Full speed mode
    • Operating temperature: -40~+85 industrial temperature range
    • 2.4GHz RF transceiver embedded
    • Embeds internal RF matching circuit
    • RF link data rate: 250Kbps as specified in 802.15.4
    • Sensitivity: typical value -98dBm
    • Tx output power up to +8dBm
    • Single-pin antenna interface
    • RSSI monitoring

Benefits

    • Supports Zigbee Pro feature set
    • Thread support
    • Compliant with: Zigbee Home Automation, Zigbee Light Link, Zigbee Human Interface, and Zigbee RF4CE profiles
    • A range of reference applications for RF4CE remote controls and ZLL lighting systems to enable fast product developmen

Applications

    • Smart Home
    • Smart Lighting
    • Home/Building Automation
    • Smart Grid
    • Intelligent Logistics/Transportation/City
    • Consumer Electronics
    • Industrial Control
    • Health Care

Deliverables

  • RTL source code
  • SW source code
  • Technical Documents, and integration support
  • Reference code for Zigbee stack
  • Reference design, and SDK
Highly-integrated SoC solution, the Zigbee chip is a true 2.4GHz SoC solution.

Bluetooth Dual Mode v4.2 Baseband IP

This Bluetooth Dual Mode v4.2 Digital Baseband IP is the design data base of a production Bluetooth Dual Mode SoC shipped in smart phones. The Baseband IP is compliant with Bluetooth Classic and Low Energy standards including BT 2.1 + BT 3.0 + EDR + BT 4.2 and BLE. Firmware source code is supplied to enable interface into protocol Stack SW at the HCI layer through UART and I2S. The A2DP offloading can also be performed with audio data transferred from Host over PCM or I2C of Stereo Audio Data samples (44.1 or 48 Khz) to/from the IP. Data can be transferred in burst mode over the PCM / I2S interface in order to achieve significant host power consumption improvements during A2DP playback. The IP embeds support of modified SBC encoding and decoding for Wideband speech. The Whole processing is performed internally and does not require dedicated processing from Host side. An optional DSP (CoolFlux) is integrated into the audio path to provide audio processing capabilities from Wide-Band Audio Codec implementation to MP3 and noise cancellation.

Features

      • High Volume Silicon Proven
      • Extracted from Design Data Base of production chip
      • Fully compliant to BT standard
      • Support of Bluetooth Low energy (BLE)
      • Support of Basic Rate and Enhanced Data rate (2 and 3 Mb/s)
      • Supports Scatternet topologies
      • S(eSCO)/S/S, M(eSCO)/S/S and M/S(eSCO)/S
      • HCI interface to 3rd party Dual Mode Protocol Stacks
      • Available integrated with Bluetooth Dual Mode v4.2 RF Transceiver IP

Deliverables

      • Source Code Delivery with rights to modify
      • Schematics
      • Certification Certificates
      • Chip Test program
      • KGD

Bluetooth Dual Mode SoC White Box IP

Description

A unique opportunity to licence the "white box source code" design data base of a Tier 1 semiconductor's high volume mass production BT4.0 Dual Mode "SoC" that has been shipped in Tier 1 OEM products. This IP is delivered as the complete chip design data base enabling internalization, customization and porting of the design to future process nodes. The IP comes with all certification certificates and SW and the design data base can be TO and in volume production in under 6 months of purchase. The commercial terms are single NRE payment, no royalties, unlimited usage, making it a very cost effective, low risk, BT Dual Mode technology access. 20141214102017-bt-dualmode-chip-block-diagram

Features

    • Dual Band 2.4/5 Ghz RF with integrated PA
    • Certified in Tier 1 handset shipped in high volume
    • Best-in-class IOT with comprehensive coverage
    • Ultra low power consumption with innovative host offloading features
    • RF design includes best in class cellular blocker and innovative LTE & BT Co-Existence
    • Integrated SMPS with direct battery connection
    • Flexible firmware host partitioning architecture catering to different customer system partitioning
    • Reduced PCB footprint with minimal external components

Benefits

    • A mass production chip that is available as a white box IP license with modification rights and unlimited usage

Applications

    • IoT
    • M2M
    • Cellular
    • Automotive

Deliverables

  • Design Data Base of chip
  • Schematics
  • Layout
  • Source Code
  • Certification Certificates
  • Chip Test program