Wireless Connectivity IP
ZigBee Sub1 Ghz 802.15.4 RF IP
ZigBee Transceiver PHY IP
Description
The modulation and spreading functions for the O-QPSK PHYs are processed through 3 steps. First, each 4 bits are gathered to represent 1 symbol which has a value from 0 to 15. Second, each symbol is used to select among 16 PN sequences called chip. Finally, each chip is modulated using O-QPSK with half-sine pulse shaping.
Once a preamble is detected, the Start of Frame Delimiter (SFD), frame length, and other receiver status information is sent to the upper layer. Additionally, the payload data is written to the received data buffer to create the PSDU packet, which is transferred to the MAC layer when requested. The PHY notifies the MAC layer for arrival of MAC Protocol Data Unit (MPDU) along with the LQI information via an interrupt. If a valid preamble is not detected, it gives feedback to the packet time error detection block to restart the energy detection process. The design includes ED and LQI circuits to support CCA modes by MAC defined in IEEE 802.15.4. The design includes a standard 32-bit AHB-lite, slave interface version 3.0, with registers as defined in the Register Description section of the Datasheet. Features
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- Low power transceiver PHY IP for ZigBee applications, compliant with IEEE 802.15.4 standard.
- Efficient demodulator with frame synchronization and frequency offset compensation.
- Supports 2 MHz IF input (reconfigurable on request).
- Offset-QPSK (OQPSK)
- Chip rate: 2000 kchips/sec
- Bit rate: 250 kbits/sec
- Symbol rate: 62.5 ksymbols/sec
- Spreading sequence: 16-ary orthogonal
- Support a carrier frequency offset (CFO) up to 250 KHz
- Sampling frequency: 8 MHz (reconfigurable on request)
- Uses single-bit limiter (8-bit ADC version available on request)
- AHB-Lite bus interface (other interfaces available on request)
Applications
- Home automation
- Health care
- Smart energy
- Smart metering Utility Network (SUN)
Deliverables
- Synthesizable Verilog
- System Model (Matlab) and documentation
- Verilog Test Benches
- Documentation
DVB S2/S Satellite Tuner SoC White Box IP
DVB T/C Demodulator SoC White Box IP
DVB S2X/T2/C Demod+H264 STB SoC White Box IP
DVB S2X Satellite Full Band Capture Tuner Demodulator SoC White Box IP
Highly-integrated SoC solution, the Zigbee chip is a true 2.4GHz SoC solution.
Bluetooth Dual Mode v4.2 RF Transceiver IP
Highly-integrated SoC solution, the Zigbee chip is a true 2.4GHz SoC solution.
Bluetooth Dual Mode v4.2 Baseband IP
This Bluetooth Dual Mode v4.2 Digital Baseband IP is the design data base of a production Bluetooth Dual Mode SoC shipped in smart phones. The Baseband IP is compliant with Bluetooth Classic and Low Energy standards including BT 2.1 + BT 3.0 + EDR + BT 4.2 and BLE. Firmware source code is supplied to enable interface into protocol Stack SW at the HCI layer through UART and I2S.
The A2DP offloading can also be performed with audio data transferred from Host over PCM or I2C of Stereo Audio Data samples (44.1 or 48 Khz) to/from the IP. Data can be transferred in burst mode over the PCM / I2S interface in order to achieve significant host power consumption improvements during A2DP playback. The IP embeds support of modified SBC encoding and decoding for Wideband speech. The Whole processing is performed internally and does not require dedicated processing from Host side.
An optional DSP (CoolFlux) is integrated into the audio path to provide audio processing capabilities from Wide-Band Audio Codec implementation to MP3 and noise cancellation.
Features
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- High Volume Silicon Proven
- Extracted from Design Data Base of production chip
- Fully compliant to BT standard
- Support of Bluetooth Low energy (BLE)
- Support of Basic Rate and Enhanced Data rate (2 and 3 Mb/s)
- Supports Scatternet topologies
- S(eSCO)/S/S, M(eSCO)/S/S and M/S(eSCO)/S
- HCI interface to 3rd party Dual Mode Protocol Stacks
- Available integrated with Bluetooth Dual Mode v4.2 RF Transceiver IP
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Deliverables
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- Source Code Delivery with rights to modify
- Schematics
- Certification Certificates
- Chip Test program
- KGD
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Bluetooth Dual Mode SoC White Box IP
Description
A unique opportunity to licence the "white box source code" design data base of a Tier 1 semiconductor's high volume mass production BT4.0 Dual Mode "SoC" that has been shipped in Tier 1 OEM products. This IP is delivered as the complete chip design data base enabling internalization, customization and porting of the design to future process nodes. The IP comes with all certification certificates and SW and the design data base can be TO and in volume production in under 6 months of purchase. The commercial terms are single NRE payment, no royalties, unlimited usage, making it a very cost effective, low risk, BT Dual Mode technology access. Features
- Dual Band 2.4/5 Ghz RF with integrated PA
- Certified in Tier 1 handset shipped in high volume
- Best-in-class IOT with comprehensive coverage
- Ultra low power consumption with innovative host offloading features
- RF design includes best in class cellular blocker and innovative LTE & BT Co-Existence
- Integrated SMPS with direct battery connection
- Flexible firmware host partitioning architecture catering to different customer system partitioning
- Reduced PCB footprint with minimal external components
Benefits
- A mass production chip that is available as a white box IP license with modification rights and unlimited usage
Applications
- IoT
- M2M
- Cellular
- Automotive
Deliverables
- Design Data Base of chip
- Schematics
- Layout
- Source Code
- Certification Certificates
- Chip Test program