8259-Interupt Controller IP

Description

The D8259 is a soft Core of Programmable Interrupt Controller. It is fully compatible with the 82C59A device. Our efficient IP core can manage up to 8-vectored priority interrupts for the processor. Moreover, you can also program it to cascade and gain up to 64 vectored interrupts. And if it's not enough, you can always get more than 64 vectored interrupts. Just program our IP Core to the Poll Command Mode. The D8259 can operate in all 82C59A modes and it supports all 82C59A features. The D8259 Package includes fully automated testbench. Thanks to complete set of tests, you can easily validate the whole package at each stage of SoC design flow.

Features

    • 8 vectored priority interrupts
    • Up to sixty-four vectored priority interrupts with cascading
    • Support for all 82C59A modes features
    • MCS-80/85 and 8088/8086 processor modes
    • Fully nested mode and special fully nested mode
    • Special mask mode
    • Buffered mode
    • Pool command mode
    • Cascade mode with master or slave selection
    • Automatic end-of-interrupt mode
    • Specific and non-specific end-of-interrupt commands
    • Automatic and Specific Rotation
    • Edge and level triggered interrupt input modes
    • Reading of interrupt request register (IIR) and in-service register (ISR) through data bus
    • Fully synthesizable HDL Source Code
    • Static design and no internal tri-states

Applications

    • Embedded microprocessor boards

Deliverables

  • VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF
  • VHDL & VERILOG test bench environment Active-HDL automatic simulation macros
  • ModelSim automatic simulation macros Tests with reference responses
  • Technical documentation Installation notes HDL core specification Datasheet
  • Synthesis scripts Example application Technical support

SLIC IP

Description

This is a SLIC device specifically designed for wireless local loop (WLL) and ISDN terminal adaptors (ISDN-TA) and VoIP applications. One of the distinctive characteristic of this device is the ability to operate with a single supply voltage (from 5.5 V to 12 V) and self generate the negative battery by means of an on chip DC/DC converter controller that drives an external MOS switch. The battery level is properly adjusted depending on the operating mode. A useful characteristic forthese applications is the integrated ringing GENERATOR. The control interface is a parallel type with open drain output and 3.3 V logic levels. Constant current feed can be set from 20 mA to 40 mA. Off-hook detection threshold is programmable from 5 mA to 9 mA. The metering pulses are generated on chip starting from two logic signals (0 and 3.3 V) one define the metering pulse frequency and the other the metering pulse duration. An on chip circuit then provides the proper shaping and filtering. Metering pulse amplitude and shaping (rising and decay time) can be programmed by external components. A dedicated cancellation circuit avoid possible codec input saturation due to metering pulse echo.

Features

    • Monochip subscriber line interface circuit (SLIC) optimised for WLL and VoIP applications
    • Implement all key features of the BORSHT function
    • Single supply (5.5 V to 12 V)
    • Built in DC/DC converter controller
    • Soft battery reversal with programmable transition time.
    • On-hook transmission.
    • Programmable off-hook detector threshold
    • Metering pulse generation and filter
    • Integrated ringing
    • Integrated ring trip
    • Parallel control interface (3.3 V logic level)
    • Programmable constant current feed
    • Surface mount package
    • Integrated thermal protection
    • Dual gain value option
    • BCD III S, 90 V technology
    • -40 to +85 °C operating range

Deliverables

  • Configurable RTL Code
  • HDL based test bench and behavioral models
  • Test cases
  • Protocol checkers, bus watchers and performance monitors
  • Configurable synthesis shell
  • Documentation
  • Design Guide
  • Verification Guide
  • Synthesis Guide

LVDS TX PHY IP

Description

This is a physical layer for LVDS TX. It consists of six differential channels and supports 167.86 Mbps to 1.25Gbps data rate.

Features

    • LVDS Tx compliant with EIA/TIA-644 LVDS
    • Up to 1.25Gbps/lane data rate
    • 3.3V/1.2V power supply
    • Configurable common mode voltage
    • Supports reduced swing mode
    • Supports loop back test mode
    • Supports metal option TBD
    • Used devices - Core voltage RVT-NMOS/PMOS, Diode, 3.3V OD-NMOS/PMOS, Diode, NMOS cap, BJT, Un-silicided poly resister

Deliverables

  • Datasheet
  • Integration guideline
  • GDSII or Phantom GDSII
  • Layer map table
  • CDL netlist for LVS
  • LEF
  • Verilog behavior model
  • Liberty timing model
  • DRC/LVS/ERC results