LVDS TX PHY IP

LVDS TX PHY IP

Description

This is a physical layer for LVDS TX. It consists of six differential channels and supports 167.86 Mbps to 1.25Gbps data rate.

Features

    • LVDS Tx compliant with EIA/TIA-644 LVDS
    • Up to 1.25Gbps/lane data rate
    • 3.3V/1.2V power supply
    • Configurable common mode voltage
    • Supports reduced swing mode
    • Supports loop back test mode
    • Supports metal option TBD
    • Used devices - Core voltage RVT-NMOS/PMOS, Diode, 3.3V OD-NMOS/PMOS, Diode, NMOS cap, BJT, Un-silicided poly resister

Deliverables

  • Datasheet
  • Integration guideline
  • GDSII or Phantom GDSII
  • Layer map table
  • CDL netlist for LVS
  • LEF
  • Verilog behavior model
  • Liberty timing model
  • DRC/LVS/ERC results