USB3.0 PCIe3 SATA3 Combo PHY IP

Description

The MiPHYA c4.0 macrocell is extracted from production chips, it implements the lower (physical) layer protocols of the following standards:
  • USB 3.0 SuperSpeed
  • PCI-e 3.0
  • SATA gen1/2/3
Data transmission and reception are provided over a dual differential pair CABLE. The TX (transmit) and RX (receive) serial channels operate plesiochronously (NRZ). The macro-cell can be used in Host or Device applications.

Features

    • Serial transceiver (physical layer)
    • Serializer and deserializer
    • Direct support for USB3.0 SuperSpeed at 5.0 Gbit/s
    • Direct support for 6.0 Gbit/s SATA
    • 2.5 and 5.0 Gbit/s PCI Express operation
    • Embedded oscillator
    • High-performance PLL
    • 20-bit parallel interface
    • SSC modulation
    • Comma detect to provide word alignment of incoming serial stream
    • Requires DC-balanced encoding scheme
    • Integrated impedance adaptation to transmission line characteristics
    • Serial TX buffer with programmabl amplitude, pre-emphasis and slew rate
    • OOB signaling
    • JTAG test access port allows Internal loop-back for self-test
    • Random pattern auto-test
    • 1.1 V power supply -5 / +10%
    • 1.8 or 2.5 V power supply +/- 10%
Integrated BIST allows:
    • Self test of the macrocell in loop back mode at Gigabit rate on production testers
    • Self test of the macrocell at system level, either in internal/external loop back mode or between different chips in transmission mode

Applications

    • USB 3.0 SuperSpeed
    • PCI-e 3.0
    • SATA gen1/2/3 Transmission schemes encoding octets a 10-bit code groups to form a DC-balanced stream
    • High-performance backplane interconnect

Deliverables

  • GDSII layout and layer map files with Abstract with size and pin locations (lef)
  • Verilog-a, CDL, encrypted Spectra netlist with Verification reports and environment Test cases, bring-up plans, coverage Re- ports
  • System level simulation model for channel simulations

USB 2.0 Super Speed host Controller IP

Description

USB 2.0 Host controller is a highly configurable core and implements the USB 2.0 Host functionality that can be interfaced with third party USB 2.0 PHY’s. USB2.0 Host controller core is part of USB3.0 family of cores.
Host Controller core is architected with an high performance DMA engine based on xHCI specification. The core can be configured to support full-fledged USB 2.0 host controller based higher performance xHCI specification for use in standard PCIe-USB bus adaptors/chip sets or be configured with a subset of features for embedded applications requiring limited host functionality.
The controller has a very simple application interface which can be easily adapted to standard on-chip-bus interfaces such as AXI,AHB, OCP as well as other standard off-chip interconnects making it easy to be integrated in a wide range of applications.
The controller's simple, configurable and modular architecture is independent of application logic, PHY designs, implementation tools and, most importantly, the target technology.
    • Configurable Options
    • Optional USB3.0 Core for Superspeed Support
    • Application Interface – AHB, AXI, PCIe
    • Configurable Buffer Sizes
    • xHCI Engine with configurable number of device slots, interrupters, root hub ports, configurable scratchpad support, optional support for host initiated stream data movement and optional debug capability etc
    • Also available - USB 2.0 Audio , USB 2.0 HID,USB 2.0 OTG Controller and USB2.0 Device Controller and Device
 

Features

    • Compliant with xHCI Rev1.0
    • Compliant with USB Specification Rev 2.0
    • Supports HS/FS/LS mode of operation.
    • Asynchronous clocking between Host Controller and Application logic.
    • Supports Aggressive Low Power Management
    • Configurable PHY Interface: 8/16 UTMI, ULPI.
    • Flexible User Application Logic
    • Can be adapted by any SoC / OCBinterface / offchip interconnects – such asAHB, AXI, PCIe
    • Configurable Datawidth: 32, 64, 128 bit.
    • Simple Register Interface for internal Register Access.
    • Support for various Hardware and Software Configurability regarding Core characteristics.
    • Easy migration path for Superspeed Support

Benefits

    • Highly modular and configurable design
    • Layered architecture
    • Fully synchronous design
    • Supports both sync and async reset
    • Clearly demarked clock domains
    • Extensive clock gating support
    • Multiple Power Well Support
    • Software control for key features

Applications

    • Human Interface Devices like keyboards,
    • mousses or game peripherals
    • Mass Storage devices like flash disks, mp3 or mp4 players
    • GPS navigation systems
    • Digital Cameras
    • Cellular phones
    • Audio devices like microphones and speakers
    • Printers
    • Scanners

Deliverables

  • Configurable RTL Code
  • HDL based test bench and behavioral models
  • Test cases
  • Protocol checkers, bus watchers and performance monitors
  • Configurable synthesis shell
  • HDL core specification
  • Datasheet
  • Synthesis scripts
  • Example application
  • Technical support

USB 2.0 Audio Design Platform IP

Description

    • The USB 2.0 Audio Design platform is a complete ,integrated solution,designed to be used in USB based Audio Devices such as speaker and microphones. You can use it in various applications,like portable flash memories, digital audio players, card readers and digital cameras.
This includes :
  • DUSB2 peripheral controller designed to support 12 Mb/S full speed and 480 Mb/S high speed serial data transmission rates.
  • DP8051XP ultra high performance ,speed optimized fully customizable 8051 8 bit microcontroller with built in debug IP core.
  • Audio device stack optimized software for DP8051XP 8bit CPU.
  • FPGA board with ready to use , pre programmed example USB stereo speakers applications.
  • Supports UTMI Transceiver Macrocell interface.

Features

    • Full complience with the USB 2.0 specifications
    • Full speed 12 Mbps operation
    • High speed 480 Mbps operation
    • Suspend and resume power management functions
    • 100% software compatible with 8051 industry standard
    • Upto 256 bytes of internal data memory
    • Up to 64k bytes of internal or external program Memory
    • User programmable program memory wait states solution for wide range of memories speed
    • User programmable External data memory wait state solution for wide range of memories speed
    • Fully syntheziable, static synchronous design with positive edge clocking and no internal tri states
    • Scan test ready

      Benefits

    • Fully Certified
    • Shipped in millions of products
    • Supper Low Power Consumption

Deliverables

  • Verilog/Vhdl Source Code
  • Modelsim automatic simulation macros
  • Audio device software stack source code
  • FPGA board with ready to use preprogrammed example application
  • Synthesis script
  • DataSheet

USB 3.1 PHY IP

Description

T2M a leading provider of High Speed Serial Interface IPs solutions, provides 10Gbps SerDes in leading 28nm process which supports USB 3.1 PMA specification. The transceiver is integrated with low jitter 10GHz PLL which offers excellent phase noise margin. This IP also supports 5 Gbps USB 3.0 standard.
Technology Option
  • GF 28SLP
  • TSMC 65G
  • TSMC 28HPC (0.9V)
Power Management
  • 4 Defined Power States
  • Active Current Sensing
  • Maximum Power Level Enumeration

Features

  • USB 3.1 with backward compatibility (USB 3.0) Meeting all specs of USB 3.1
  • Parallel data width 8 Bits with QUAD configuration ( 4 TX and 4RX ), Single Lane Configuration (1 Tx, 1Rx)
  • Support Signal loss & receiver detection
  • Programmable 3 tap & de-emphasis, Support 1m cable
  • Optimized Metal Stakes for Lower NRE expense ( 6020+LB )
  • 1.0V supply to support -40 to 125 deg.C
  • CDR logic for better data alignment and locking, Complaint with PIPE 4.2
  • High speed low jitter 10GHz PLL
  • Applications

  • Storage
  • Switches and Bridge
  • Surveillance Camera
  • Digital Still Camera
  • 4K/8K TV

    Deliverables

  • GDSII layout and layer map files with Abstract with size and pin locations (lef)
  • verilog-a, CDL, encrypted Spectra netlist and Verification reports and environment
  • Test cases, bring-up plans, coverage Reports , Timing views (.lib)
  • Synthesis environment/Scripts , System level simulation model for channel simulations

USB 3.0 Host controller IP

Description

The USB 3.0 Host controller is a highly configurable core and implements the USB 3.0 Host functionality that can be interfaced with third party USB 3.0 PHY's. The Host Controller core is architected with an optional high performance DMA engine based on xHCI specification. The core can be configured to support full fledged xHCI implementations for use in standard PCIe-USB bus adaptors/chip sets or be configured with a subset of features for embedded applications requiring limited host functionality. The Host Controller core is carefully partitioned to support standard power management schemes which include extensive clock gating and multiple power wells for aggressive power savings required for mobile and handheld applications. The controller has a very simple application interface which can be easily adapted to standard on-chip-bus interfaces such as AXI, AHB, OCP as well as other standard off-chip interconnects making it easy to be integrated in a wide range of applications. The controller's simple, configurable and modular architecture is independent of application logic, PHY designs, implementation tools and most importantly, the target technology.

Features

    • Compliant with xHCI Rev1.0
    • Compliant with USB3.0 Specification Rev1.0
    • Implements Phy Logical/ Link / Protocol Layers.
    • Asynchronous clocking between Host Controller and Application logic
    • Supports Aggressive Low Power Management
    • Configurable core frequency: 125, 250, 500 Mhz.
    • Configurable PIPE Interface: 8, 16, 32 bit.
    • Flexible User Application Logic
    • Can be adapted by any SoC / OCB interface / offchip interconnects – such as AHB, AXI, PCIe
    • Configurable Datawidth: 32, 64, 128 bit.
    • Simple Register Interface for internal Register Access.
    • Support for various Hardware and Software Configurability regarding Core characteristics.
    • Optional USB2.0 Core for Backward Compatibility
    • Application Interface – AHB, AXI, PCIe
    • Configurable Buffer Sizes
    • xHCI Engine with configurable number of device slots, interrupters, root hub ports, configurable scratchpad support, optional support for host initiated stream data movement and optional debug capability etc

Benefits

    • Highly modular and configurable design
    • Layered architecture
    • Fully synchronous design
    • Supports both sync and async reset
    • Clearly demarked clock domains
    • Extensive clock gating support
    • Multiple Power Well Support
    • Software control for key features
    • Multiple loop backs for debug

Deliverables

  • Design RTL Code
  • Verification Environment
  • Tests suites
  • Synthesis Environments & scripts
  • Design Guide
  • Verification Guide
  • Synthesis Guide