The USB 3.0 Host controller is a highly configurable core and implements the USB 3.0 Host functionality that can be interfaced with third party USB 3.0 PHY's. The Host Controller core is architected with an optional high performance DMA engine based on xHCI specification. The core can be configured to support full fledged xHCI implementations for use in standard PCIe-USB bus adaptors/chip sets or be configured with a subset of features for embedded applications requiring limited host functionality.
The Host Controller core is carefully partitioned to support standard power management schemes which include extensive clock gating and multiple power wells for aggressive power savings required for mobile and handheld applications. The controller has a very simple application interface which can be easily adapted to standard on-chip-bus interfaces such as AXI, AHB, OCP as well as other standard off-chip interconnects making it easy to be integrated in a wide range of applications.
The controller's simple, configurable and modular architecture is independent of application logic, PHY designs, implementation tools and most importantly, the target technology.
- Compliant with xHCI Rev1.0
- Compliant with USB3.0 Specification Rev1.0
- Implements Phy Logical/ Link / Protocol Layers.
- Asynchronous clocking between Host Controller and Application logic
- Supports Aggressive Low Power Management
- Configurable core frequency: 125, 250, 500 Mhz.
- Configurable PIPE Interface: 8, 16, 32 bit.
- Flexible User Application Logic
- Can be adapted by any SoC / OCB interface / offchip interconnects – such as AHB, AXI, PCIe
- Configurable Datawidth: 32, 64, 128 bit.
- Simple Register Interface for internal Register Access.
- Support for various Hardware and Software Configurability regarding Core characteristics.
- Optional USB2.0 Core for Backward Compatibility
- Application Interface – AHB, AXI, PCIe
- Configurable Buffer Sizes
- xHCI Engine with configurable number of device slots, interrupters, root hub ports, configurable scratchpad support, optional support for host initiated stream data movement and optional debug capability etc
- Highly modular and configurable design
- Layered architecture
- Fully synchronous design
- Supports both sync and async reset
- Clearly demarked clock domains
- Extensive clock gating support
- Multiple Power Well Support
- Software control for key features
- Multiple loop backs for debug
- Design RTL Code
- Verification Environment
- Tests suites
- Synthesis Environments & scripts
- Design Guide
- Verification Guide
- Synthesis Guide