USB 2.0 PHY IP

USB 3.1 PHY IP

Description

T2M a leading provider of High Speed Serial Interface IPs solutions, provides 10Gbps SerDes in leading 28nm process which supports USB 3.1 PMA specification. The transceiver is integrated with low jitter 10GHz PLL which offers excellent phase noise margin. This IP also supports 5 Gbps USB 3.0 standard.
Technology Option
  • GF 28SLP
  • TSMC 65G
  • TSMC 28HPC (0.9V)
Power Management
  • 4 Defined Power States
  • Active Current Sensing
  • Maximum Power Level Enumeration

Features

  • USB 3.1 with backward compatibility (USB 3.0) Meeting all specs of USB 3.1
  • Parallel data width 8 Bits with QUAD configuration ( 4 TX and 4RX ), Single Lane Configuration (1 Tx, 1Rx)
  • Support Signal loss & receiver detection
  • Programmable 3 tap & de-emphasis, Support 1m cable
  • Optimized Metal Stakes for Lower NRE expense ( 6020+LB )
  • 1.0V supply to support -40 to 125 deg.C
  • CDR logic for better data alignment and locking, Complaint with PIPE 4.2
  • High speed low jitter 10GHz PLL

    • Applications

  • Storage
  • Switches and Bridge
  • Surveillance Camera
  • Digital Still Camera
  • 4K/8K TV

    Deliverables

  • GDSII layout and layer map files with Abstract with size and pin locations (lef)
  • verilog-a, CDL, encrypted Spectra netlist and Verification reports and environment
  • Test cases, bring-up plans, coverage Reports , Timing views (.lib)
  • Synthesis environment/Scripts , System level simulation model for channel simulations