Designing First Time Right RTL

  • Verilog, VHDL
  • Protocol Specification
  • Micro-Architecture
  • Low Power and Re-usable RTL design with Minimum Area
  • RTL Designing for Speed
  • Synthesis and Timing Clean RTL
  • LINT, Spyglass, CDC Checks
  • Development of Block Level TB
  • Coverage Analysis
  • Clock-tree Friendly clock structures