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Incise has great team in Emulation and FPGA design have hands-on experience doing the following activities at several of our clients.

• Floor plan and power plan CTS, HFNS, Routing,
• Scan Insertion and Stitching, Leakage Optimization, ECOs
• STA Signoff using Cadence and Synopsys flows
• Lower technology nodes such as 10nm to 180nm

• LVS ,DRC, Antenna, DFM, ERC & ESD
• IR Drop Analysis
• TCL Based Automation
• Calibre, Assura

• ARM Hard Platform, Bluetooth SOC, Wireless SOC, DVB-H/T, Generic ARC Control Platform , Ultra Wide Band SOC

• Full Custom Memory Design
• Memory Characterization & Re-Characterization
• Memory Timing, Area, Power Optimization
• SRAM, DPRAM, ROM, Register File

• DLL, PLL, Oscillator, Power Regulators, DC-DC Converters
• Layout Migration

• 1KB to 10 MB SRAM, DPRAM, ROM
• Layout Migration 65nm to 28nm

• Architecture, Specification and Micro-Architecture development
• Reusable RTL Design for Low Power, Minimum Area and Maximum Speed
• Synthesis, Timing Clean RTL, CDC, LINT
• Verilog, VHDL, System Verilog

• RTL Integration, 3rd Party IP Integration
• ARM, ARC, 8 Bit Processors, Starcore
• Timing constraints, Low power Clocking, Analog + Digital SOC
• FPGA to ASIC Migration, FPGA Prototyping & Validation

• UFS 2.0 , EMMC, SD USB 3.0 Interlaken ,DDR3.0, PCI Express, AHB, AXI ,MIPI, UniPro, M-PHY, ARM, Bluetooth , Wireless, DVB-H/T , Generic ARC Control Platform

• System Verilog, UVM, OVM
• Specman, TCL, PERL
• Constrained Random TB
• Assertions, Functional Coverage, Code Coverage, Formal Verification

• C++/C/Assembly Based Verification
• System Verilog, UVM, OVM
• Gate Level Verification
• System Level Verification/ FPGA Verification
• Coverage Driven

• UFS 2.0 , EMMC, SD USB 3.0 Interlaken ,DDR3.0, PCI Express, AHB, AXI ,MIPI, UniPro, M-PHY, ARM, Bluetooth , Wireless, DVB-H/T , Generic ARC Control Platform