Semiconductor

Analog and Mixed Signal

We have strong design and development teams with varied expertise across analog designs. We have expertise across various nodes and all the aspects of analog design right from Architecture development, circuit design, Layout development till final full chip release. Our teams have time and again proven their mettle through constant release of chips successfully mass produced. We have strong track record for successfully developing various Analog IPs like

• ADC,DAC,PLL,Data Converters
• Power Management Blocks
• Bias/Reference Generators,LDOs
• Transmitters,Receivers
• MIDI,PHY and HDMI interfaces

Memory Design

We are an expert team in Foundation IP design, development and service, with proven track record of first pass silicon success. We look at complete IP solutions from spec definition to silicon validation, the entire process of IP development and qualification. Our robust design enablers and unmatched automated design qualification methodologies ensure fist time silicon success of the products developed. Our Memory development activities Include Development of

• Memory Compilers
• New product development
• Re-qualification
• Design optimization
• Feature addition and customization
• Custom Memories
• Performance Specific architecture
• Custom Register files and Multiport memories
• Multi-megabit SRAM
• TCAMs

Standard Cell and IO Services

 We are an expert team in Foundation IP design, development and service, with proven track record of first pass silicon success. We look at complete IP solutions from spec definition to silicon validation, the entire process of IP development and qualification. Our roust design enablers and unmatched automated design qualification methodologies ensure fist time silicon success of the product developed. We support the following Standard cell developments

• Standard Cells
• HS,HD Libraries
• Power Management Libraries
• Architecture development
• New product developments
• Re-qualification
• Design optimization
• Library Migration/Porting

On the IO front we support the following Development of various IO libraries ranging from

• GPIO Libraries
• HDMI and MIDI
• Custom IOs
• High Speed SERDES

• Floor plan and power plan CTS, HFNS, Routing,
• Scan Insertion and Stitching, Leakage Optimization, ECOs
• STA Signoff using Cadence and Synopsys flows
• Lower technology nodes such as 10nm to 180nm

• LVS ,DRC, Antenna, DFM, ERC & ESD
• IR Drop Analysis
• TCL Based Automation
• Calibre, Assura

• ARM Hard Platform, Bluetooth SOC, Wireless SOC, DVB-H/T, Generic ARC Control Platform , Ultra Wide Band SOC

• System Verilog, UVM, OVM
• Specman, TCL, PERL
• Constrained Random TB
• Assertions, Functional Coverage, Code Coverage, Formal Verification

• C++/C/Assembly Based Verification
• System Verilog, UVM, OVM
• Gate Level Verification
• System Level Verification/ FPGA Verification
• Coverage Driven

• UFS 2.0 , EMMC, SD USB 3.0 Interlaken ,DDR3.0, PCI Express, AHB, AXI ,MIPI, UniPro, M-PHY, ARM, Bluetooth , Wireless, DVB-H/T , Generic ARC Control Platform

• Architecture, Specification and Micro-Architecture development
• Reusable RTL Design for Low Power, Minimum Area and Maximum Speed
• Synthesis, Timing Clean RTL, CDC, LINT
• Verilog, VHDL, System Verilog

• RTL Integration, 3rd Party IP Integration
• ARM, ARC, 8 Bit Processors, Starcore
• Timing constraints, Low power Clocking, Analog + Digital SOC
• FPGA to ASIC Migration, FPGA Prototyping & Validation

• UFS 2.0 , EMMC, SD USB 3.0 Interlaken ,DDR3.0, PCI Express, AHB, AXI ,MIPI, UniPro, M-PHY, ARM, Bluetooth , Wireless, DVB-H/T , Generic ARC Control Platform