DVB S2/S Satellite Tuner SoC White Box IP


This satellite tuner is a direct-conversion (zero IF) receiver for digital TV Broadcasting. On the RF input, there is a variable gain, low-noise amplifier (VGLNA). The RF gain is monitored by an automatic gain control (AGC) circuit to ensure an optimal signal level for the two mixers. Each mixer, which down-converts the signal to the baseband, is followed by an AGCcontrolled VGA, a low-pass filter and a second VGA. The local oscillator (LO) signals are provided by an integrated fractional-N phase locked loop (PLL), which contains an on-chip voltage-controlled oscillator (VCO) meeting stringent phase noise requirements.

The PLL loop filter is partly integrated. The LO frequencies are programmable between 950 MHz and 2150 MHz. The comparison frequency for the phase-frequency detector (PFD) is generated by dividing the crystal oscillator reference frequency. The crystal frequency may be within the range 15 MHz to 31 MHz depending on the application.



    • High volume production proven in leading STBs
    • RF-to-Baseband direct conversion architecture
    • Single 3.3-V DC supply, low consumption
    • Outstanding performance in heavily loaded spectrum conditions
    • Input frequency range: 950 to 2150 MHz
    • Supports 1 to 60 Msymb/s using internal filter
    • Specific operating mode for symbol rates up to 220 Msymb/s
    • RF-AGC or channel-AGC support
    • Extremely low-phase noise, compliant with DVB-S2 requirements using fractional-N Synthesizer
    • Low external component count
    • Flexible crystal frequency output to drive the demodulator and/or other tuner ICs
    • Continuously variable gain
    • Programmable 6 to 50 MHz cut-off frequency (Butterworth 5th-order baseband filters)
    • Compatible with 5-V and 3.3-V I2C bus


    • Direct broadcasting satellite (DBS), satellite modems: BPSK, QPSK, 8PSK, 16/32 APSK modulations
    • Input frequency range: 950 to 2150 MHz
    • Extremely low-phase noise, compliant with DVB-S1 and DVB-S2
    • Set-top boxes, PCTV and iDTV
    • Outdoor units


  • White Box IP – source Code delivery
  • RTL source code
  • Software source code
  • Technical documents
  • Test vectors and simulation model
  • Host emulation test environment
  • Porting & Integration support

DVB T/C Demodulator SoC White Box IP


The V0367 inherits the functionality of the industry-leading enhanced V0362 terrestrial and V0297E cable demodulators in one single advanced combo receiver.

The V0367 COFDM section of the receiver is fully compliant with the DVB-T standard framing structure, channel coding and modulation. The symbol, timing and carrier recovery loops are completely digital and tailored to comply with state-of-the-art RF down-converting tuner devices.

The V0367 DVB-C section is a complete QAM (quadrature amplitude modulation) demodulation and FEC (forward error correction) solution that performs IF-to-transport stream block processing of QAM signals.

The demodulator provides error-corrected MPEG transport-stream outputs which can be routed to the transport sub-system.



Combined DVB-T/-C receiver

    • DVB-T demodulation
    • DVB-C demodulation
    • I²C serial bus interface
    • Compatible with low- to high-IF tuners
    • Flexible clock management
    • ADC for RF signal strength indicator
    • Flexible and DVB-CI compliant TS output
    • Ultra-compact TQFP64 package


    • This highly integrated SoC helps to reduce board area and manufacturing cost, allowing low cost and small size STBs to be designed for either DVB-C or DVB-T networks.
    • Flexible AGC for different signal environments.
    • Best-in-class, low-power standby mode, to meet emerging energy standards for STBs.
    • Clock-rate management and improvements in channel acquisition efficiency enable a powerefficient standby mode.
    • Enables fast and seamless integration in complex digital TV systems such as iDTV, set-top boxes or PCTV dongles.


  • Verilog Source RTL Code plus Simulation Environment
  • Verification Environment
  • Integration support
  • Datasheet/Integration Guide/Verification Guide

DVB S2X/T2/C Demod+H264 STB SoC White Box IP


The device integrates leading ARM® application processors architecture and GPU to provide thin client platforms, or interactive broadcast set top-box (STB) platforms, supporting the latest middleware and software solutions.

The device’s integrated carrier-grade fully-offloaded Wi-Fi MAC allows full HD video streaming throughout the home, making it the ideal device for Wi-Fi client boxes.

The device supports full HD, high-efficiency video coding (HEVC) reducing memory bandwidth for video distribution.


    • Multi-core ARM® Cortex™ application CPU delivering up to 6000 DMIPS
    • High-performance GPU for fluid 3D graphics (ARM® Mali™-400)
    • DDR3/3L 32-bit interface running at up to 1066 MHz (DDR3-2133)
    • HEVC Main10 @ L4.1 (1080p60)
    • H.264 AVC, @ L4.2 (1080p60)
    • H.264 MVC and SHP @ L4.1 (1080p30L30R)
    • VC-1, MPEG4, MPEG2, AVS, AVS+
    • Web-based content decoding: Flash, DivX, Xvid, MJPEG, WMV
    • High-quality Faroudja video post-processing, including support for Blu-ray HDR10 content
    • HDMI-TX 1.4b/2.0a @ 1080p60 with HDCP 1.4 and 2.2
    • Supporting 802.11.a/b/g/n/ac wave 2
    • Up to 4 x 4 MIMO
    • Supports single-band 5 GHz or 2.4 GHz, or dual-band switchable
    • Generation 4 security for concurrent CA/DRM support, including schemes such as NSK 2.1, SVP, DTCP-IP, PlayReady, DVB-CPCM, DivX and Marlin
    • 1 x USB 2.0
    • 1 x USB 3.0
    • 1 x SD card
    • 1 x eMMC
    • 1 x Smartcard
    • 1 x Ethernet GMAC/RGMII
    • 4 x Input transport streams


    • IP Client & Broadcast Platform - UHD 4Kp60
    • Server and Client Platform - UHD 60 fps
    • HEVC IP Client, Satellite or Cable Server - Dual HD/4K
    • Broadcast HD, HEVC, S2X/C/I


  • Verilog Source RTL Code plus Simulation Environment
  • C Source Code
  • Physical Design scripts - Synopsys synthesis
  • Hardware simulation test bench with regression test suit
  • Reference platform drivers

DVB S2X Satellite Full Band Capture Tuner Demodulator SoC White Box IP


The iD135 has been designed for Satellite Broadband applications, leveraging Ka-band and multi-spot beam technology carried by the latest high-throughput satellites (HTSs).

The iD135 has been designed to enable single-carrier usage of HTS transponders. The device implements two high-symbol-rate (HSR) demodulators compliant with Annex M of the DVB-S2/S2X specification EN 302 307, and provides full HW support for network clock recovery (NCR) in order to enable external return-channel modulators.

The iD135 may be used in standard broadcast environments as an 8-channel DVB-S2/S2X receiver enabling multi-channel distribution and/or fast channel change scenarios.


Two high-symbol-rate (HSR) demodulators:

  • Maximum baud rate 500 Msymbol/s
  • Up to two slices each
  • DVB-S2/S2X and Annex M compliant
  • Up to 8 multi-standard demodulators:
  • S/S2/S2X/DTV
  • Integrated full-band tuners and ADCs
  • High-speed digital multiplexer to connect any tuner to any demodulator
  • NCR PLL support

Flexible transport stream processor:

  • PID filtering, PCR re-stamping and re-labelling, GSE label filtering
  • TS merger (multiplex)
  • Channel bonding
  • Low power consumption
  • Wake-on-network PID or GSE label
  • Fast auto scan
  • Signal monitoring, spectral analysis, bit error rate test and reporting


  • Crystal oscillator
  • I2C serial bus interface, including private repeater for optional LNA
  • TS, 8 serial, 2 parallel or multiplexed
  • JTAG for boundary scan
  • DiSEqC 1.x and DiSEqC2.x compatible receiver, 22-kHz
  • FSK modem
  • Flexible GPIOs and interrupts


  • Single rail supply with inbuilt SMPSs for internal supply generation
  • Fine-grained power management
  • VQFPN-mr 13x13 mm2 package, RoHS
  • Temperature range -40 to +85 °C ambient


  • Verilog Source RTL Code plus Simulation Environment
  • Technical Documents


  • Verilog Source RTL Code plus Simulation Environment
  • C Source Code
  • Physical Design scripts - Synopsys synthesis
  • Hardware simulation test bench with regression test suit
  • Reference platform drivers