Job Locations: Delhi/NCR
Total vacancies: 3

– Define and develop new capabilities & HW/SW tools to enable acceleration of RTL and improve emulation/FPGA model usability for pre-Silicon and post-Silicon    functional validation as well as SW development/validation.

– Create emulation models from RTL/Netlist.

– Develop hardware collateral to be integrated with the Palladium/FPGA emulation model.

– Create and execute Test plans targeting Sub-systems and SoC level.

– System level performance analysis, bandwidth, latency across interconnect.

– Experience with Speed Bridge Integration and perform real time testing.

– Experience in integrating Acceleration VIPs and perform co-emulation.

– Experience in Palladium or Zebu Platforms

– Automate and increase process efficiency

To apply for this position, please either enter your details along with the updated resume in the right hand side panel OR send your updated resume directly to with current CTC, expected CTC and notice period details. Our team will contact you for further details.