Job Locations: Hyderabad
Total vacancies: 8

  • Strong fundamentals in physical design verification using Calibre nmDRC/nmLVS
  • Perform and debug DRC, LVS, Antenna, DFM, ERC and ESD checks on blocks and top-level design.
  • TVF basics and automation of DesignREV using TCL scripting is a must.
  • Understanding of custom PERC decks based on internal flow and debug.
  • PnR Flow knowledge is a plus, not mandatory

To apply for this position, please either enter your details along with the updated resume in the right hand side panel OR send your updated resume directly to with current CTC, expected CTC and notice period details. Our team will contact you for further details.