Skills: System Verilog
Job Locations: Hyderabad
Total vacancies: 0

– Requires some decent understanding of perl/sed/any shell scripting 
– Makefile would be plus. 
– This work requires simulation/synthesis understanding. 
– Understanding of Verilog/systemveriloig code is a must. 
– Syntheis (is optional). If you have it is good other wise .. it can be taught during the job. 
– The candidate should be enthusiastic and willing to go beyond and learn the stuff to perform. 
– Can be in range of 1-5 years experience. 

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