Job Locations: Hyderabad
Total vacancies: 2
– BS / MS with 5+ years of experience.
– Expertise in the following languages: Perl, Tcl and Verilog
– Expertise in the use of make
– Experience in engineering flow development.
– Exposure to FPGA compile tools, Xilinx tools a must.
– Good SW debug and problem solving skills.
– Knowledge of FPGA details a definite plus
To apply for this position, please either enter your details along with the updated resume in the right hand side panel OR send your updated resume directly to firstname.lastname@example.org with current CTC, expected CTC and notice period details. Our team will contact you for further details.