Skills: UVM/OVM,Verilog,PCIe,Perl,Shell Scripting
Job Locations: Delhi/NCR
Total vacancies: 0

·         Fluent in System Verilog HVL and hands-on on Verilog HDL. [Minimum 1.5 to 4 years of Experience]

·         Hands on experience in developing source code with reasonable complexity.

·         Hands on experience in deriving the features for the block / cluster under verification starting from scratch or from the legacy.

·         Hands on experience in developing feature list, testplan and testbench strategies for the DUTs.

·         Working knowledge of EDA tools(NCSim,VCS, QuestaSim)

·         Knowledge of industry standard protocols like Ethernet, PCIe, MIPI, DDR, AXI-AHB Bus or any other protocol will be added advantage.

·         Verification of complex RTL design IP / complex FPGA design / SoC at module level and system level.

·         Experience in methodology Test Harness, OVM/VMM/UVM [Min 2 Years of experience in any of the methodology]

·         Working knowledge of Unix, shell or Perl programming. It would be added advantage if hands-on with Clearcase and Clearquest tools.

·         Proven track record of executing at least 1-2 projects in individual capacity.

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