Incise offers:
Incise provides expert verification Services to world wide customers in Wireless, Automotive, Networking domains. Incise has strong expertise in integration & verification of Memory controllers , Communication protocols, Wireless IPs/SoCs at ASIC/FPGA level. Team has strong expertise in latest UVM/OVM based verification flows.
Key Areas of Association:
- IP Verification
- SOC Verification
- Automation of Legacy Verification Environment
- Migration to System Verilog Based Testbench
- System Level Verification (Use case verification)
- VIP Development
- CPU Verification & Validation
- Gate Level SOC Verification
- FPGA Prototyping & Validation
- Silicon Validation, Chip bringup,
- Device driver development and Testing
Why INCISE:
- Strong domain knowledge in Wireless, Automotive & Networking domains
- Deep system level knowledge of all kind of memory controllers integration & Verification.
- Strong expertise in chip to chip communication IP Integration & Verification
KEY EXPERTISE:
- System Verilog, Verilog, VHDL
- UVM, OVM, VMM,
- C based SOC Verification
- TCL, PERL, Makefile, Automation of complete SOC
- SVA (System Verilog Assertion) based Verification for Protocol Compliance
- Coverage Driven Verification, Constrained Random Verification
- Black box Verification, (Verification without golden Specification)
INCISE SUCCESS STORIES
SOC Expertise
- Design and Verification DVB-H/T, Pay TV Conditional Access chip sets
- Design and Verification of Automotive/Networking chip Sets
- Design and Verification of Wireless (2G,3G, 4G) GSM based chip
- Design and Verification of Bluetooth low energy SOC (Ultra Low Power)
- Design and Verification of Hearing Aid Microcontroller (Ultra Low power)
IP Expertise
LPDDR2, RLDRAM 2/3, Flash Memory, Flash Security, UFS 2.0, MIPI M-PHY, UNIPRO, Interlaken, Ethernet, USB 2.0, USB 3.0,Power Management, DCDC Controller,Reed Solomon, AES, SHA, DMA, USART, I2C, SPI, GPIO, IOMUX, Modem, Audio Codec, Clock & Reset, Viterbi, IR Receiver, WDOG, PWM, ARM,ARC, MIPS Processors, Cache, MMU…
Bus Interfaces
AXI 3.0, AHB System, APB, Wishbone
Tools Expertise
All Industry Standard Tools: Synopsys (VCS & DVE, Formality, Spyglass), Cadence (ncSIM & Simvision, Conformal, HAL Check) Mentor Graphics ( Questa Sim & vsim).
Deliverables
– Verified Design Specification
– Detailed test guide
– Detailed Test plan & test strategy
– Verified RTL
– Detailed signed checklist
– Reusable UVM based Testbench (VIP)
– Self Testing Direct, Random testcases
– Environment Automation Scripts
– Functional Coverage Report
– Code Coverage report
– Formal Equivalence, Spyglass Check