16950-UART IP


The D16950 is a soft core of a Universal Asynchronous Receiver/Transmitter (UART), functionally identical to the OX16C950. It allows serial transmission in two modes: UART and FIFO. In the FIFO mode, internal FIFOs are activated, allowing 128 bytes (plus 3 bits of error data per byte in the RCVR FIFO) to be stored in both receive and transmit modes. Our efficient Core performs a serial-to-parallel conversion on data characters received from a peripheral device or a MODEM, but also parallel-to-serial conversion on data characters received from the CPU. The processor can read a complete status of the UART at any time during the functional operation. Status information reported includes the type and condition of transfer operations being performed by the UART, as well as any error conditions (parity, overrun, framing or break interrupt). The D16950 includes a programmable baud rate GENERATOR, which is capable to divide the timing reference clock input by divisors of 1 to (216-1) and produce a n × clock for driving the internal transmitter logic. Provisions are also included to use this n × clock to drive the receiver logic. We also equipped our core with a complete MODEM-control capability and a processor-interrupt system. Interrupts can be programmed in accordance to your requirements, minimizing computing required to handle the communications link. The D16950 core includes all (16450, 16550, 16650 and 16750) features and additional functions. The D16950 has ICR registers, which give additional capabilities of UART work configuration. The data transmission may be synchronized by an external clock connected to the RI (for receiver and transmitter) or the DSR (only for receiver) pin. The NMR register allows to enable a 9-bit mode transmission, with or without special character. Writing and reading from/to FIFO may be controlled by trigger level registers. Trigger level registers may be set any value from 1 to 127. In the FIFO mode, there is a selectable autoflow control feature, that can significantly reduce software overload and automatically increase the system efficiency, by controlling serial data flow, through the RTS output and the CTS input signals. The Core is perfect for applications, where the UART core and the microcontroller are clocked by the same clock signal and are implemented inside the same ASIC or FPGA chip. Nevertheless, it's also a proprietary solution for a standalone implementation, where several UARTs are required to be implemented inside a single chip and driven by some off-chip devices. Thanks to a universal interface, the D16950 core implementation and verification are very simple, just by eliminating a number of clock trees in the complete system. As all our UART Cores, the D16950 includes fully automated testbench with complete set of tests, allowing easy package validation at each stage of SoC design flow. This efficient solution is a technology independent design, that can be implemented in a variety of process technologies.


    • Software compatible with 16450, 16550,16650,16750 and 16950 UARTs
    • Configuration capability
    • Separate configurable BAUD clock line
    • Majority Voting Logic
    • Two modes of operation: UART mode and FIFO mode
    • In the FIFO mode transmitter and receiver are each buffered with 128 byte FIFO to reduce the number of interrupts presented to the CPU
    • In UART mode receiver and transmitter are double buffered to eliminate a need for precise synchronization between the CPU and serial data
    • Configurable FIFO size up to 512 levels
    • Adds or deletes standard asynchronous communication bits (start, stop and parity) to or from the serial data
    • Independently controlled transmit, receive, line status and data set interrupts
    • False start bit detection
    • 16 bit programmable baud GENERATOR
    • Independent receiver clock input
    • MODEM control functions (CTS, RTS, DSR, DTR, RI, DCD)
    • Programmable Hardware Flow Control through RTS and CTS
    • Programmable Flow Control using DTR and DSR
    • Programmable in-band Flow Control using XON/XOFF
    • Programmable special characters detection
    • Trigger levels for TX and RX FIFO
    • Interrupts and automatic in-band and out-off-band flow control
    • Fully programmable serial-interface characteristics:
    • 5-, 6-, 7-, 8- or 9-bit characters
    • Even, ODD, or no-parity bit generation and detection
    • 1-, 1.5-, or 2-stop bit generation
    • Internal baud generator
    • Detection of bad data in receiver FIFO
    • Clock prescaler from 1 to 31,875
    • Enhanced isochronous clock option
    • 9- bit data mode
    • Software reset
    • Complete status reporting capabilities
    • Line break GENERATION and detection. Internal diagnostic capabilities:
    • Loop-back controls for communications link fault isolation
    • Break, parity, overrun, framing error simulation
    • Full prioritized interrupt system controls
    • Available system interface wrappers:
    • AMBA - APB Bus
    • Altera Avalon Bus
    • Xilinx OPB Bus
    • Fully synthesizable
    • Static synchronous design and no internal tri-states


    • D-16950


    • Serial Data communications applications
    • Modem interface
    • Embedded microprocessor boards


  • Source code:
  • VHDL Source Code or/and
  • VERILOG Source Code or/and
  • Encrypted, or plain text EDIF
  • VHDL & VERILOG test bench environment
  • Active-HDL automatic simulation macros
  • ModelSim automatic simulation macros
  • Tests with reference responses
  • Technical documentation
  • Installation notes
  • HDL core specification
  • Datasheet
  • Synthesis scripts
  • Example application
  • Technical support
  • IP Core implementation support
  • 3 months maintenance
  • Delivery the IP Core updates, minor and major versions changes
  • Delivery the documentation updates
  • PHONE& email support

Tech Specs