SMART Card Interface IP


The DSMART is a fast, versatile and cost-competitive core intended for smart card reader applications. It provides a communication interface with a smart card, based on ISO 7816-3/EMV4.2 requirements. DCD’s IP Core implements the hardware support for both T0 character oriented protocol and T1 block oriented protocol. It’s been designed to combine highly reduced CPU utilization and low area consumption, it is able to activate and deactivate cards, perform resets, handle ATR reception and many additional features. Configuration options enable user to adjust the DSMART to his needs and choose the proprietary options, which will be the most suitable for his design. Data transfer to and from the host system can be interrupt-driven or executed through Direct Memory Access (DMA). The automatic convention detection and decoding mechanism ensure the exact result regardless of the used convention. Elementary Time Unit (ETU) - time duration of the one bit is decoded from the received ATR interface byte and generated automatically. The card clock divider provides non-gated clock with a wide range of possible frequencies. There’s been also a special power down modeimplemented, in which the card clock is being hold in two possible states, depending on the card parameter. Error signaling and character repetition are automatic for the T0 protocol. The DSMART incorporates also an optional CRC/LRC hardware checking and generation mechanism which gives the convention independent result. The received CRC/LRC is not stored in the FIFO, but can be read in a case of CRC/LRC error. Also the optional block length counter provides security of the DMA block transfer and automatic CRC/LRC, subjoining with a manual affixing option. The special block mode handles block transfer automatically. Status and error registers provide necessary information about the FIFO state, errors and card events.


    • Compatible with the ISO 7816-3: 2006 and EMV 4.1 standard
    • Support for asynchronous Smart Cards
    • Dual configurable length FIFO with two programmable thresholds
    • Card detection input
    • Software-configurable interrupts
    • Automatic convention detection and decoding
    • Programmable non-gated card clock generator
    • Automatic ETU generator
    • DMA support for transmit and receive
    • Hardware CRC and LRC calculations
    • Card power down mode with clock stop high and clock stop low possibility
    • Special fast block mode for T1 protocol (optional)
    • CRC/LRC hardware generation and checking
    • Byte counter with automatic CRC/LRC affixing(optional)
    • No inertial tri-state buffers
    • Fully synchronous synthesizable design


    • General purpose smart card readers
    • SO-7816 / EMV Bridges
    • Personal Wireless devices & SIM Readers in Telecom
    • Payphones and vending machines
    • Personal identification
    • Satellite TV security
    • Health care records storage


  • VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF
  • VHDL & VERILOG test bench environment Active-HDL automatic simulation macros
  • ModelSim automatic simulation macros Tests with reference responses
  • Technical documentation Installation notes HDL core specification Datasheet
  • Synthesis scripts Example application Technical support