Description

DCD’s IP Core is a technology independent design that can be implemented in a variety of process technologies. The DQSPI system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. The system can be configured as a master or a slave device. Data rates as high as CLK/2, when other vendors’ solutions offer just CLK/8. Clock control logic allows a selection of clock polarity, phase and a choice of four fundamentally different clocking protocols to accommodate most available synchronous serial peripheral devices.

When the SPI is configured as a master, software selects bit rates for the serial clock. The DQSPI automatically drive selected by SSCR (Slave Select Control Register) slave select outputs (SS7O – SS0O) and address SPI slave device to exchange serially shifted data. Error?detection logic is included to support interprocessor communications.

A write collision detector indicates when an attempt is made to write data to the serial shift register while a transfer is in progress. A multiple-master mode fault detector automatically disables DQSPI output drivers, if more than one SPI device simultaneously attempts to become bus master. The DQSPI supports two DMA modes: single transfer and multi?transfer. These modes allow DQSPI to interface to higher performance DMA units, which can interleave their transfers between CPU CYCLESor execute multi-ple byte transfers. DQSPI is fully customizable, which means it is delivered in the exact configuration to meet users’ requirements.