Charge Pump PLL (CMOS40) IP
Description
On the basis of its architecture its belongs to the class of Charge Pump PLLs. The key blocks in this architecture are mentioned in the following sections.
Phase/Frequency Detector
This block compares the phase difference between the corresponding rising edges of INFIN(buffered version of the Input Frequency Divider output) and FBCLK (buffered clock output from the Loop Frequency Divider), by generating voltage pulses with widths proportional to the input phase error.
Charge Pump and Loop Filter
Charge Pump converts the voltage pulses from the Phase/Frequency Detector to current pulses, which charge the Loop Filter and generate the Control Voltage for the Voltage Controlled Oscillator.
Voltage Controlled Oscillator
This is the oscillator inside the PLL, which produces a frequency output (FVCO) proportional to the input control voltage.Loop Frequency Divider Frequency Divider is present within the PLL for dividing VCO frequency (FVCO) by a factor called the Loop Division Factor (LDF). The output of this block is the FBCLK.
Input Frequency Divider
This Frequency Divider divides the PLL input frequency by a factor called the Input Division Factor (IDF). The output of this block is INFIN.
Output Frequency Divider
PLL output PHI is generated by dividing the FVCOBY2 clock (VCO clock divided by 2) by a factor called Output Division Factor (ODF). The divider that divides the FVCOBY2 to generate PHI is called Output Frequency Divider.
Lock Circuit
LOCKP signal is asserted high when the PLL enters the state of Coarse Lock, in which the average output frequency (for last 64 cycles of INFIN) is within ±10% (approximately) of the desired frequency. LOCKP signal is refreshed after every 64 cycles of INFIN. This is generated based on the result of the comparison of number of FBCLK cycles in a window of 58 INFIN cycles. The different cases generated after comparison are the following: If LOCKP is at L, then it goes to H in the next refresh cycle, if the number of FBCLK cycles in the 58 cycle INFIN window is 52 to 64. Otherwise, LOCKP stays at L. If LOCKP is at H, then it goes to L in the next refresh cycle, if the number of FBCLK cycles in 58 cycle INFIN window is less than 48 or higher than 68. Otherwise, LOCKP stays at H.
Features

 Input frequency: 6 MHz  350 MHz
 VCO frequency (FVCO): 1000 MHz  2000 MHz
 Output frequency (PHI): 7.93 MHz  1000 MHz
 Area: 0.1499259 mm2
 Maximum power: 5.46 mW
Applications
 Used in frequency synthesis applications