CAN-FD Controller IP

CAN-FD Controller IP

The DCAN FD is a standalone controller for the Controller Area Network (CAN), widely used in automotive and industrial applications. It conforms to Bosch CAN 2.0B specification (2.0B Active) and CAN FD (flexible data-rate). The improved proto- col overcomes standard CAN limits: data can be transmitted faster than with 1 Mbit/s and the pay- load (data field) is up to 64 byte long and limited to 8 byte anymore. When only one node is transmit- ting, the bit-rate can be increased, because no nodes need to be synchronized. Of course, before the transmission of the ACK slot bit, the nodes  need to be re-synchronized. The core has a simple CPU interface (8/16/32 bit configurable data width), with small or big endian addressing  scheme. Hardware message filtering and 128 byte receive FIFO enable back-to-back message recep- tion, with minimum CPU load. The DCAN FD is provided as HDL source code, allowing target use  in FPGA or ASIC technologies.
Features
      • Designed in accordance to ISO 11898-1:2015
      • Supports CAN 2.0B and CAN FD frames
      • Support up to 64 bytes data frames
      • Flexible data rates supported
      • 8/16/32-bit CPU slave interface with small or big endianness
      • Simple interface allows easy connection to CPU
      • Supports both standard (11-bit identifier) and extended (29 bit identifier) frames
      • Data rate up to 8 Mbps
      • Hardware message filtering (dual/single filter)
      • 128 byte receive FIFO and transmit buffer
      • Overload frame is generated on FIFO overflow
      • Normal & Listen Only Mode
      • Transceiver Delay Compensation up to three data bit long
      • Single Shot transmission
      • Ability to abort transmission
      • Readable error counters

Deliverables

Source code

    • VHDL Source Code or/and
    • VERILOG Source Code or/and
    • FPGA Netlist

VHDL /VERILOG test bench environment

      • Active-HDL automatic simulation macros
      • NCSim automatic simulation macros
      • ModelSim automatic simulation macros
      • Tests with reference responses

Technical documentation

        • Installation notes
        • HDL core specification
        • Datasheet

Synthesis scripts

Example application

Technical support

IP Core implementation support

        • 3 months maintenance
        • Delivery of the IP Core and documentation updates, minor and major versions changes
        • Phone & email support