Description
The DHDLC IP core is used for controlling HDLC/SDLC transmission frame, designed to be used with 8-bit MCU, like DP8051/DP80390. It allows to save MCU time wasted for handling HDLC/SDLC features like bit stuffing, address recognition or CRC computation. The DHDLC has implemented FIFO buffer, for both, receiver and transmitter.
The DHDLC IP core is full synchronous with one clock domain design. All parameters are configurable by CPU. But there is also capability for setting parameters by modification constants in source file. There is no need to wasting silicon resources for unused features and constant settings.
Features
-
- Two separate receiver and transmitter interfaces.
- Two separate, configurable FIFO buffers for receiver and transmitter
- Bit stuffing and unstuffing
- Address recognition for receiver and address insertion for transmitter
- Two or one byte address field
- RC-16 and CRC-32 computation and checking
- Collision detect
- Byte alignment error detection
- Programmable number of bits for idle detection
- NRZI coding support
- Shared flags, shared zeros support
- Pad fill with flags option
- Transmitter clock generation
- 8-bit CPU interface
- Interrupt output for handling control flags and FIFOs’ filling
- Configurable core parameters
Benefits
Applications
-
- CPU based applications with serial interface based on HDLC/SDLC protocol
- Telecommunication
Deliverables
-
- Source code:
- VHDL Source Code or/and
- VERILOG Source Code or/and
- Encrypted, or plain text EDIF
- VHDL & VERILOG test bench environment
- Active-HDL automatic simulation macros
- ModelSim automatic simulation macros
- Tests with reference responses
- Technical documentation
- Installation notes
- HDL core specification
- Datasheet
- Synthesis scripts
- Example application
- Technical support
- IP Core implementation support
- 3 months maintenance
- Delivery the IP Core updates, minor and major versions changes
- Delivery the documentation updates
- Phone & email support
Tech Specs
