The I2C Controller IP is compact low power and scalable IP core. I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices. It is most suitable for applications requiring communication over short distance between many devices.
The standard VCI interface provided in I2C IP core makes integration easy into any design.I2C controller IP core is fully synthesizable core suitable for different process. The IP core is portable to an ASIC or a FPGA. It has been validated on Xilinx platform. Along with the IP core, we will provide complete test environment with constraint randomized test cases and our full support during integration.
- Compliant to version 2.1 of the I2C Bus standard
- System Bus Interface - VCI
- Optional Bus Interface - AHB, APB, OCP
- Data transfers up to 400 Kbps
- Supports Master Transmitter Mode - Serial data output on SDA and clock on SCL output
- Supports Master Receiver Mode - Serial data is received via SDA while SCL outputs the serial clock
- Single master mode
- Supports up to eight slave devices with unique address
- Verilog source / encrypted code of the IP core
- Verilog Test environment and test scripts
- Synthesis constraints and scripts
- Documentation – Design , Verification & Integration guide
- FPGA validation platform (Xilinx / Altera
- The host interface is a 32 bit VCI slave interface. This interface is used to integrate the IP core within the SoC design and to read/ write the internal registers of the core.
Control and Status Registers
- This block consists of I2C registers for data transfer and control and status information. These registers are programmable through VCI interface.
- This functional block controls the generation of I2C clock from the IP core for data transfer.
- This block consists of state machines for sending command and data bytes on to the I2C bus.
Transmit and Receive
- This block has the buffers and the control logic for transmitting and receiving the data through host and I2C interfaces.