Controller

CAN-FD Controller IP

The DCAN FD is a standalone controller for the Controller Area Network (CAN), widely used in automotive and industrial applications. It conforms to Bosch CAN 2.0B specification (2.0B Active) and CAN FD (flexible data-rate). The improved proto- col overcomes standard CAN limits: data can be transmitted faster than with 1 Mbit/s and the pay- load (data field) is up to 64 byte long and limited to 8 byte anymore. When only one node is transmit- ting, the bit-rate can be increased, because no nodes need to be synchronized. Of course, before the transmission of the ACK slot bit, the nodes  need to be re-synchronized. The core has a simple CPU interface (8/16/32 bit configurable data width), with small or big endian addressing  scheme. Hardware message filtering and 128 byte receive FIFO enable back-to-back message recep- tion, with minimum CPU load. The DCAN FD is provided as HDL source code, allowing target use  in FPGA or ASIC technologies.
Features
      • Designed in accordance to ISO 11898-1:2015
      • Supports CAN 2.0B and CAN FD frames
      • Support up to 64 bytes data frames
      • Flexible data rates supported
      • 8/16/32-bit CPU slave interface with small or big endianness
      • Simple interface allows easy connection to CPU
      • Supports both standard (11-bit identifier) and extended (29 bit identifier) frames
      • Data rate up to 8 Mbps
      • Hardware message filtering (dual/single filter)
      • 128 byte receive FIFO and transmit buffer
      • Overload frame is generated on FIFO overflow
      • Normal & Listen Only Mode
      • Transceiver Delay Compensation up to three data bit long
      • Single Shot transmission
      • Ability to abort transmission
      • Readable error counters

Deliverables

Source code

    • VHDL Source Code or/and
    • VERILOG Source Code or/and
    • FPGA Netlist

VHDL /VERILOG test bench environment

      • Active-HDL automatic simulation macros
      • NCSim automatic simulation macros
      • ModelSim automatic simulation macros
      • Tests with reference responses

Technical documentation

        • Installation notes
        • HDL core specification
        • Datasheet

Synthesis scripts

Example application

Technical support

IP Core implementation support

        • 3 months maintenance
        • Delivery of the IP Core and documentation updates, minor and major versions changes
        • Phone & email support

I2S Controller Core IP

Description

I2S Controller is a highly configurable core for use in I2S compliant CODECs. It provides a simple glueless interface to industry standard audio devices. This digital audio controller core is compliant to the dominant audio standard protocol I2S. The core is optimally architected for high performance, low latency and small silicon footprint. The core is provided with the generic processor bus interface on the system side enabling the core to be used in a variety of applications including SoC applications. The core's simple and configurable architecture is independent of implementation tools and, most importantly, target technologies. I2S core is a cost effective, end-to-end solution that allows the licensees to easily migrate to FPGA,Gate array and Standard cell technologies optimally. I2S core solution leverages years of experience in creating reusable designs for Ethernet, PCI-X, SPI-4 and Hyper Transport technologies to offer lowest risk in terms of compliance and interoperability. I2S core has been tested for Amba AHB 32-bit wide interface on the system side and DMA channel support for FIFO data transfer has also been provided in this setup. I2S Controller is a highly configurable core for use in I2S compliant CODECs. It provides a simple glueless interface to industry standard audio devices. This digital audio controller core is compliant to the dominant audio standard protocol I2S. The core is optimally architected for high performance, low latency and small silicon footprint. The core is provided with the generic processor bus interface on the system side enabling the core to be used in a variety of applications including SoC applications. The core's simple and configurable architecture is independent of implementation tools and, most importantly, target technologies. I2S core is a cost effective, end-to-end solution that allows the licensees to easily migrate to FPGA,Gate array and Standard cell technologies optimally. I2S core solution leverages years of experience in creating reusable designs for Ethernet, PCI-X, SPI-4 and Hyper Transport technologies to offer lowest risk in terms of compliance and interoperability. I2S core has been tested for Amba AHB 32-bit wide interface on the system side and DMA channel support for FIFO data transfer has also been provided in this setup.

Features

    • Compliant to I2S Serial Bus protocol
    • Supports full duplex flow control - 1 PCM playback channel and 1 record channel
    • Supports 8/16/18/20/24/32 bit DAC/ADC resolution through software configuration
    • Supports both 256 and 384 sampling frequency (fs) operating mode
    • Support 8/16/32/48/96/192/44.1/88.2/176.4 KHz audio sample frequency
    • Processor Bus 8/16/32-bit wide Interface on system side
    • Supports 1/2/4 samples per 32 bit packing option through Software configuration
    • Fully synchronous design with serial clock and system clock
    • Interrupt Support for FIFO data read/write
    • Programmable FIFO thresholds
    • Loop back mode for testing purposes

Benefits

    • Configurable Options
    • Playback and Record FIFO depths
    • Playback and Record FIFO widths
    • Processor bus width – 8/16/32
    • Synchronous and asynchronous reset

Deliverables

  • Parameterized RTL Code
  • Automated and parameterized test bench
  • Test cases
  • Synthesis environment/scripts
  • Design document
  • Acceptance Test Bench Specification (ATS)
  • Software specification

LIN Bus IP

Description

The DLIN is a soft core of the Local Interconnect Network (LIN). This interface is a serial communication protocol, designed primarily to be used in automotive applications. Compared to CAN, LIN is slower, but thanks to its simplicity, is much more cost effective. Our Core is ideal for a communication in intelligent sensors and actuators, where the bandwidth and versatility of CAN is not required. The DLIN core provides an interface between a microprocessor/microcontroller and a LIN bus. It can work as master or slave LIN node, depending on a work mode, determined by the microprocessor/microcontroller. DCD's controller supports transmission speed between 1 and 20kb/s, which allows it to transmit and receive LIN messages compatible to LIN 1.3. LIN 2.1 and the newest 2.2. The reported information status includes the type and condition of transfer operations being performed by the DLIN, as well as a wide range of LIN error conditions (overrun, framing, parity, timeout). Our Core includes programmable timer, which allows to detect timeout and synchronization error. The DLIN is described at RTL level, empowering the target use in FPGA and ASIC technologies LIN (Local Interconnect Network) is a serial communication protocol, which was created to provide a cost efficient bus communication. The LIN standard is developed by LIN consortium (More). It includes the specification of the transmission medium, the interface between development tools, the transmission protocol and the interfaces for software programming. LIN has been created to decrease costs of automotive networks and replace more expensive CAN in simple application (sensors or actuators). The LIN device can be implemented as a master or as a slave node. Transmission is initiated by Master Node, which sends the data frame to Slaves Nodes (maximum 15) throat one wire bus.

Features

    • Conforms with LIN 1.2, LIN 2.1 and LIN 2.2 specification.
    • Automatic LIN Header handling
    • Automatic Re-synchronization
    • Data rate between 1Kbit/s and 20 Kbit/s
    • Master and Slave work mode
    • Time-out detection
    • Extended error detection
    • “Break-in-data” support
    • Available system interface wrappers:
    • AMBA - APB Bus
    • Altera Avalon Bus
    • Xilinx OPB Bus

Applications

    • Automotive, industrial
    • Embedded communication systems

Deliverables

  • Source code
  • Technical support
  • Example application
  • Synthesis scripts
  • Datasheet
  • HDL core specification
  • Installation notes
  • Technical documentation
  • Tests with reference responses
  • ModelSim automatic simulation macros
  • Active-HDL automatic simulation macros
  • VHDL & VERILOG test bench environment
  • Encrypted, or plain text EDIF
  • VERILOG Source Code or/and
  • VHDL Source Code or/and

LCD/TFT Display Controller IP

HDLC Controller IP

Description

The DHDLC IP core is used for controlling HDLC/SDLC transmission frame, designed to be used with 8-bit MCU, like DP8051/DP80390. It allows to save MCU time wasted for handling HDLC/SDLC features like bit stuffing, address recognition or CRC computation. The DHDLC has implemented FIFO buffer, for both, receiver and transmitter. The DHDLC IP core is full synchronous with one clock domain design. All parameters are configurable by CPU. But there is also capability for setting parameters by modification constants in source file. There is no need to wasting silicon resources for unused features and constant settings.

Features

    • Two separate receiver and transmitter interfaces.
    • Two separate, configurable FIFO buffers for receiver and transmitter
    • Bit stuffing and unstuffing
    • Address recognition for receiver and address insertion for transmitter
    • Two or one byte address field
    • RC-16 and CRC-32 computation and checking
    • Collision detect
    • Byte alignment error detection
    • Programmable number of bits for idle detection
    • NRZI coding support
    • Shared flags, shared zeros support
    • Pad fill with flags option
    • Transmitter clock generation
    • 8-bit CPU interface
    • Interrupt output for handling control flags and FIFOs’ filling
    • Configurable core parameters

Benefits

    • D-HDLC

Applications

    • CPU based applications with serial interface based on HDLC/SDLC protocol
    • Telecommunication

Deliverables

    • Source code:
    • VHDL Source Code or/and
    • VERILOG Source Code or/and
    • Encrypted, or plain text EDIF
    • VHDL & VERILOG test bench environment
    • Active-HDL automatic simulation macros
    • ModelSim automatic simulation macros
    • Tests with reference responses
    • Technical documentation
    • Installation notes
    • HDL core specification
    • Datasheet
    • Synthesis scripts
    • Example application
    • Technical support
    • IP Core implementation support
    • 3 months maintenance
    • Delivery the IP Core updates, minor and major versions changes
    • Delivery the documentation updates
    • Phone & email support

Tech Specs

  • D-HDLC

CAN-Bus IP

Description

The DCAN is a standalone controller for the Controller Area Network (CAN), which is commonly used in automotive and industrial applications. What's most IMPORTANT, the DCAN conforms to the Bosch CAN 2.0B specification (2.0B Active). The Core has a simple CPU interface (8/16/32 bit configurable data width), with little or big endian addressing scheme. The DCAN supports both standard (11 bit identifier) and extended (29 bit identifier) frames. Hardware message filtering and 64 byte receive FIFO, enable a back-to-back message reception with a minimum CPU load. The DCAN is described at RTL level, allowing target use in FPGA or ASIC technologies. The Controller Area Network (CAN) is a advanced serial communications protocol developed by Robert Bosch GmbH. CAN protocol uses Data Link Layer and the Physical Layer in the ISO-OSI model. The CAN bus uses multi-master bus scheme with one logic bus line and equal nodes. The number of nodes is not limited by the protocol. Nodes do not have specific addresses. Instead, message identifiers are used, indicating the message content and priority of message. This also means that multicasting and broadcasting is supported by CAN. Number of nodes may be changed at run-time without disturbing the communication of the other nodes. CAN provides sophisticated error detection and error handling mechanisms and, due to differential transmission, high immunity against electromagnetic interference. Frames with errors are automatically retransmitted (except single shot transmission feature implemented in the DCAN core). Maximum data transfer rate is 1Mbps at maximum 40 m bus length when using a twisted wire pair. The bus is handled with Carrier Sense Multiple Access / Collision Detection with Non-Destructive Arbitration. This means that collision of messages is avoided by bitwise arbitration, without loss of time. CAN controller is connected to host/CPU and CAN bus transceiver, which directly connects to CAN bus line (2-wire).

Features

  • Conforms to Bosch CAN 2.0B Active
  • 8/16/32-bit CPU slave interface with little or big endianess
  • Simple interface allows easy connection to CPU
  • Data rate up to 1 Mbps
  • Hardware message filtering (dual/single filter)
  • 64 byte receive FIFO
  • One transmit buffer
  • No overload frames are generated
  • Normal & Listen Only Mode
  • Single Shot transmission
  • Ability to abort transmission
  • Readable error counters
  • Last Error Code
  • Available system interface wrappers:
    • AMBA - APB Bus
    • Altera Avalon Bus
    • Xilinx OPB Bus
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready

Benefits

 
  • D-CAN
 

Applications

  • Automotive, industrial
  • Embedded communication systems

Deliverables

    • Source code:
      • VHDL Source Code or/and
      • VERILOG Source Code or/and
      • Encrypted, or plain text EDIF
    • VHDL & VERILOG test bench environment
      • Active-HDL automatic simulation macros
      • ModelSim automatic simulation macros
      • Tests with reference responses
    • Technical documentation
      • Installation notes
      • HDL core specification
      • Datasheet
    • Synthesis scripts
    • Example application
    • Technical support
      • IP Core implementation support
      • 3 months maintenance
      • Delivery the IP Core updates, minor and major versions changes
      • Delivery the documentation updates
      • Phone & email support

Tech Specs

  • D-CAN

I2C Controller IP

Description

The I2C Controller IP is compact low power and scalable IP core. I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices. It is most suitable for applications requiring communication over short distance between many devices. The standard VCI interface provided in I2C IP core makes integration easy into any design.I2C controller IP core is fully synthesizable core suitable for different process. The IP core is portable to an ASIC or a FPGA. It has been validated on Xilinx platform. Along with the IP core, we will provide complete test environment with constraint randomized test cases and our full support during integration.

Features

    • Compliant to version 2.1 of the I2C Bus standard
    • System Bus Interface - VCI
    • Optional Bus Interface - AHB, APB, OCP
    • Data transfers up to 400 Kbps
    • Supports Master Transmitter Mode - Serial data output on SDA and clock on SCL output
    • Supports Master Receiver Mode - Serial data is received via SDA while SCL outputs the serial clock
    • Single master mode
    • Supports up to eight slave devices with unique address

Benefits

    • I2C Controller

Applications

    • I2C Controller

Deliverables

    • Verilog source / encrypted code of the IP core
    • Verilog Test environment and test scripts
    • Synthesis constraints and scripts
    • Documentation – Design , Verification & Integration guide
    • FPGA validation platform (Xilinx / Altera

Tech Specs

Host Interface

    • The host interface is a 32 bit VCI slave interface. This interface is used to integrate the IP core within the SoC design and to read/ write the internal registers of the core.

Control and Status Registers

    • This block consists of I2C registers for data transfer and control and status information. These registers are programmable through VCI interface.

Clock Generator

    • This functional block controls the generation of I2C clock from the IP core for data transfer.

Command Control

    • This block consists of state machines for sending command and data bytes on to the I2C bus.

Transmit and Receive

  • This block has the buffers and the control logic for transmitting and receiving the data through host and I2C interfaces.

I2C IP

Description

The I2C is a two-wire, bi-directional serial bus, which provides a simple and efficient method of short distance data transmission between many devices. The DI2CMS core provides an interface between a microprocessor/microcontroller and an I2C bus. It can work as a master or a slave transmitter/receiver - depending on a working mode, determined by the microprocessor/microcontroller. The DI2CMS coreincorporates all features required by the latest I2C specification, including clock synchronization, arbitration, multi-master systems and a high-speed transmission mode (the DI2CMS supports all the transmission speed modes).Built-in timer allows operation from a wide range of the clk frequencies. The DI2CMS is technology independent, that's why a VHDL or VERILOG design can be implemented in a variety of process technologies. Furthermore, it can be also completely customized in accordance to the customer's needs. The DI2CMS is delivered with fully automated testbench and complete set of tests, allowing easy package validation at each stage of SoC design flow. The I2C-bus supports any IC fabrication process (NMOS, CMOS, bipolar). Two wires, serial data (SDA) and serial clock (SCL), carry information between devices connected to the bus. Each devices is recognised by a unique address – whether it is a microcontroller, LCD driver, memory or keyboard interface. It can operate as either transmitter or receiver, depending on the function of the device. Obviously an LCD driver is only a receiver, whereas a memory can both receive and transmit data. In addition to transmitters and receivers, devices can also be considered as masters or slaves when performing data transfers (see Figures below). A master is the device which initiates a data transfer on the bus and generates the SCL clock signals. A slave is the device addressed by a master. The I2C-bus is a multi-master bus. This means that more than one device capable of controlling the bus can be connected to it. As masters are usually microcontrollers or microprocessors. i2c-ms

Features

    • Conforms to v.3.0 of the I2C specification
    • Master mode
    • Master operation
    • Master transmitter
    • Master receiver
    • Support for all transmission speeds
    • Standard (up to 100 kb/s)
    • Fast (up to 400 kb/s)
    • Fast Plus (up to 1 Mb/s)
    • High Speed (up to 3,4 Mb/s)
    • Arbitration and clock synchronization
    • Support for multi-master systems
    • Support for both 7-bit and 10-bit addressing formats on the I2C bus
    • Build-in 8-bit timer for data transfers speed adjusting
    • Slave mode
    • Slave operation
    • Slave transmitter
    • Slave receiver
    • Supports 3 transmission speed modes
    • Standard (up to 100 kb/s)
    • Fast (up to 400 kb/s)
    • Fast Plus (up to 1 Mb/s)
    • High Speed (up to 3,4 Mb/s)
    • Allows operation from a wide range of input clock frequencies
    • User-defined data setup time
    • User-defined timing (data setup, start setup, start hold, etc.)
    • Simple interface allows easy connection to microprocessor/microcontroller devices
    • Interrupt generation
    • Available system interface wrappers:
    • AMBA - APB Bus
    • Altera Avalon Bus
    • Xilinx OPB Bus
    • Fully synthesizable
    • Static synchronous design
    • Positive edge clocking and no internal tri-states
    • Scan test ready

Benefits

    • D-I2C-MS

Applications

    • Embedded microprocessor boards
    • Consumer and professional audio/video
    • Home and automotive radio
    • Low-power applications
    • Communication systems
    • Cost-effective reliable automotive systems

Deliverables

  • Source code:
  • VHDL Source Code or/and
  • VERILOG Source Code or/and
  • Encrypted, or plain text EDIF
  • VHDL & VERILOG test bench environment
  • Active-HDL automatic simulation macros
  • ModelSim automatic simulation macros
  • Tests with reference responses
  • Technical documentation
  • Installation notes
  • HDL core specification
  • Datasheet
  • Synthesis scripts
  • Example application
  • Technical suppor
  • IP Core implementation support
  • 3 months maintenance
  • Delivery the IP Core updates, minor and major versions changes
  • Delivery the documentation updates
  • Phone & email support